[AArch64] Use new reduc_plus_scal optabs, inc. for __builtins
* config/aarch64/aarch64-simd-builtins.def (reduc_splus_<mode>/VDQF, reduc_uplus_<mode>/VDQF, reduc_splus_v4sf): Remove. (reduc_plus_scal_<mode>, reduc_plus_scal_v4sf): New. * config/aarch64/aarch64-simd.md (reduc_<sur>plus_mode): Remove. (reduc_splus_<mode>, reduc_uplus_<mode>, reduc_plus_scal_<mode>): New. (reduc_<sur>plus_mode): Change SUADDV -> UNSPEC_ADDV, rename to... (aarch64_reduc_plus_internal<mode>): ...this. (reduc_<sur>plus_v2si): Change SUADDV -> UNSPEC_ADDV, rename to... (aarch64_reduc_plus_internalv2si): ...this. (reduc_splus_<mode>/V2F): Rename to... (aarch64_reduc_plus_internal<mode>): ...this. * config/aarch64/iterators.md (UNSPEC_SADDV, UNSPEC_UADDV, SUADDV): Remove. (UNSPEC_ADDV): New. (sur): Remove elements for UNSPEC_SADDV and UNSPEC_UADDV. * config/aarch64/arm_neon.h (vaddv_s8, vaddv_s16, vaddv_s32, vaddv_u8, vaddv_u16, vaddv_u32, vaddvq_s8, vaddvq_s16, vaddvq_s32, vaddvq_s64, vaddvq_u8, vaddvq_u16, vaddvq_u32, vaddvq_u64, vaddv_f32, vaddvq_f32, vaddvq_f64): Change __builtin_aarch64_reduc_[us]plus_... to __builtin_aarch64_reduc_plus_scal, remove vget_lane wrapper. From-SVN: r216738
This commit is contained in:
Alan Lawrence
Alan Lawrence
parent
d43a252e2f
commit
f5156c3ead
5 changed files with 90 additions and 53 deletions
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@ -1,3 +1,33 @@
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2014-10-27 Alan Lawrence <alan.lawrence@arm.com>
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* config/aarch64/aarch64-simd-builtins.def
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(reduc_splus_<mode>/VDQF, reduc_uplus_<mode>/VDQF, reduc_splus_v4sf):
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Remove.
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(reduc_plus_scal_<mode>, reduc_plus_scal_v4sf): New.
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* config/aarch64/aarch64-simd.md (reduc_<sur>plus_mode): Remove.
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(reduc_splus_<mode>, reduc_uplus_<mode>, reduc_plus_scal_<mode>): New.
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(reduc_<sur>plus_mode): Change SUADDV -> UNSPEC_ADDV, rename to...
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(aarch64_reduc_plus_internal<mode>): ...this.
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(reduc_<sur>plus_v2si): Change SUADDV -> UNSPEC_ADDV, rename to...
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(aarch64_reduc_plus_internalv2si): ...this.
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(reduc_splus_<mode>/V2F): Rename to...
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(aarch64_reduc_plus_internal<mode>): ...this.
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* config/aarch64/iterators.md
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(UNSPEC_SADDV, UNSPEC_UADDV, SUADDV): Remove.
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(UNSPEC_ADDV): New.
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(sur): Remove elements for UNSPEC_SADDV and UNSPEC_UADDV.
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* config/aarch64/arm_neon.h (vaddv_s8, vaddv_s16, vaddv_s32, vaddv_u8,
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vaddv_u16, vaddv_u32, vaddvq_s8, vaddvq_s16, vaddvq_s32, vaddvq_s64,
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vaddvq_u8, vaddvq_u16, vaddvq_u32, vaddvq_u64, vaddv_f32, vaddvq_f32,
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vaddvq_f64): Change __builtin_aarch64_reduc_[us]plus_... to
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__builtin_aarch64_reduc_plus_scal, remove vget_lane wrapper.
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2014-10-27 Alan Lawrence <alan.lawrence@arm.com>
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PR tree-optimization/61114
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@ -222,9 +222,8 @@
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BUILTIN_VSDQ_I (SHIFTIMM, sqshl_n, 0)
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BUILTIN_VSDQ_I (USHIFTIMM, uqshl_n, 0)
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/* Implemented by reduc_<sur>plus_<mode>. */
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BUILTIN_VALL (UNOP, reduc_splus_, 10)
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BUILTIN_VDQ (UNOP, reduc_uplus_, 10)
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/* Implemented by aarch64_reduc_plus_<mode>. */
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BUILTIN_VALL (UNOP, reduc_plus_scal_, 10)
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/* Implemented by reduc_<maxmin_uns>_<mode>. */
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BUILTIN_VDQIF (UNOP, reduc_smax_, 10)
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@ -1760,25 +1760,52 @@
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;; 'across lanes' add.
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(define_insn "reduc_<sur>plus_<mode>"
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(define_expand "reduc_plus_scal_<mode>"
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[(match_operand:<VEL> 0 "register_operand" "=w")
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(unspec:VDQ [(match_operand:VDQ 1 "register_operand" "w")]
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UNSPEC_ADDV)]
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"TARGET_SIMD"
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{
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rtx elt = GEN_INT (ENDIAN_LANE_N (<MODE>mode, 0));
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rtx scratch = gen_reg_rtx (<MODE>mode);
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emit_insn (gen_aarch64_reduc_plus_internal<mode> (scratch, operands[1]));
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emit_insn (gen_aarch64_get_lane<mode> (operands[0], scratch, elt));
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DONE;
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}
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)
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(define_expand "reduc_plus_scal_<mode>"
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[(match_operand:<VEL> 0 "register_operand" "=w")
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(match_operand:V2F 1 "register_operand" "w")]
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"TARGET_SIMD"
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{
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rtx elt = GEN_INT (ENDIAN_LANE_N (<MODE>mode, 0));
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rtx scratch = gen_reg_rtx (<MODE>mode);
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emit_insn (gen_aarch64_reduc_plus_internal<mode> (scratch, operands[1]));
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emit_insn (gen_aarch64_get_lane<mode> (operands[0], scratch, elt));
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DONE;
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}
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)
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(define_insn "aarch64_reduc_plus_internal<mode>"
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[(set (match_operand:VDQV 0 "register_operand" "=w")
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(unspec:VDQV [(match_operand:VDQV 1 "register_operand" "w")]
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SUADDV))]
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UNSPEC_ADDV))]
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"TARGET_SIMD"
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"add<VDQV:vp>\\t%<Vetype>0, %1.<Vtype>"
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[(set_attr "type" "neon_reduc_add<q>")]
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)
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(define_insn "reduc_<sur>plus_v2si"
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(define_insn "aarch64_reduc_plus_internalv2si"
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[(set (match_operand:V2SI 0 "register_operand" "=w")
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(unspec:V2SI [(match_operand:V2SI 1 "register_operand" "w")]
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SUADDV))]
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UNSPEC_ADDV))]
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"TARGET_SIMD"
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"addp\\t%0.2s, %1.2s, %1.2s"
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[(set_attr "type" "neon_reduc_add")]
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)
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(define_insn "reduc_splus_<mode>"
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(define_insn "aarch64_reduc_plus_internal<mode>"
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[(set (match_operand:V2F 0 "register_operand" "=w")
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(unspec:V2F [(match_operand:V2F 1 "register_operand" "w")]
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UNSPEC_FADDV))]
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@ -1796,14 +1823,17 @@
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[(set_attr "type" "neon_fp_reduc_add_s_q")]
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)
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(define_expand "reduc_splus_v4sf"
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[(set (match_operand:V4SF 0 "register_operand")
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(define_expand "reduc_plus_scal_v4sf"
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[(set (match_operand:SF 0 "register_operand")
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(unspec:V4SF [(match_operand:V4SF 1 "register_operand")]
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UNSPEC_FADDV))]
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"TARGET_SIMD"
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{
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emit_insn (gen_aarch64_addpv4sf (operands[0], operands[1]));
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emit_insn (gen_aarch64_addpv4sf (operands[0], operands[0]));
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rtx elt = GEN_INT (ENDIAN_LANE_N (V4SFmode, 0));
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rtx scratch = gen_reg_rtx (V4SFmode);
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emit_insn (gen_aarch64_addpv4sf (scratch, operands[1]));
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emit_insn (gen_aarch64_addpv4sf (scratch, scratch));
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emit_insn (gen_aarch64_get_lanev4sf (operands[0], scratch, elt));
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DONE;
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})
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@ -12964,121 +12964,103 @@ vaddd_u64 (uint64_t __a, uint64_t __b)
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__extension__ static __inline int8_t __attribute__ ((__always_inline__))
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vaddv_s8 (int8x8_t __a)
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{
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return vget_lane_s8 (__builtin_aarch64_reduc_splus_v8qi (__a), 0);
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return __builtin_aarch64_reduc_plus_scal_v8qi (__a);
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}
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__extension__ static __inline int16_t __attribute__ ((__always_inline__))
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vaddv_s16 (int16x4_t __a)
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{
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return vget_lane_s16 (__builtin_aarch64_reduc_splus_v4hi (__a), 0);
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return __builtin_aarch64_reduc_plus_scal_v4hi (__a);
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}
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__extension__ static __inline int32_t __attribute__ ((__always_inline__))
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vaddv_s32 (int32x2_t __a)
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{
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return vget_lane_s32 (__builtin_aarch64_reduc_splus_v2si (__a), 0);
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return __builtin_aarch64_reduc_plus_scal_v2si (__a);
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}
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__extension__ static __inline uint8_t __attribute__ ((__always_inline__))
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vaddv_u8 (uint8x8_t __a)
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{
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return vget_lane_u8 ((uint8x8_t)
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__builtin_aarch64_reduc_uplus_v8qi ((int8x8_t) __a),
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0);
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return (uint8_t) __builtin_aarch64_reduc_plus_scal_v8qi ((int8x8_t) __a);
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}
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__extension__ static __inline uint16_t __attribute__ ((__always_inline__))
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vaddv_u16 (uint16x4_t __a)
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{
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return vget_lane_u16 ((uint16x4_t)
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__builtin_aarch64_reduc_uplus_v4hi ((int16x4_t) __a),
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0);
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return (uint16_t) __builtin_aarch64_reduc_plus_scal_v4hi ((int16x4_t) __a);
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}
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__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
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vaddv_u32 (uint32x2_t __a)
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{
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return vget_lane_u32 ((uint32x2_t)
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__builtin_aarch64_reduc_uplus_v2si ((int32x2_t) __a),
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0);
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return (int32_t) __builtin_aarch64_reduc_plus_scal_v2si ((int32x2_t) __a);
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}
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__extension__ static __inline int8_t __attribute__ ((__always_inline__))
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vaddvq_s8 (int8x16_t __a)
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{
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return vgetq_lane_s8 (__builtin_aarch64_reduc_splus_v16qi (__a),
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0);
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return __builtin_aarch64_reduc_plus_scal_v16qi (__a);
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}
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__extension__ static __inline int16_t __attribute__ ((__always_inline__))
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vaddvq_s16 (int16x8_t __a)
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{
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return vgetq_lane_s16 (__builtin_aarch64_reduc_splus_v8hi (__a), 0);
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return __builtin_aarch64_reduc_plus_scal_v8hi (__a);
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}
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__extension__ static __inline int32_t __attribute__ ((__always_inline__))
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vaddvq_s32 (int32x4_t __a)
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{
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return vgetq_lane_s32 (__builtin_aarch64_reduc_splus_v4si (__a), 0);
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return __builtin_aarch64_reduc_plus_scal_v4si (__a);
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}
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__extension__ static __inline int64_t __attribute__ ((__always_inline__))
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vaddvq_s64 (int64x2_t __a)
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{
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return vgetq_lane_s64 (__builtin_aarch64_reduc_splus_v2di (__a), 0);
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return __builtin_aarch64_reduc_plus_scal_v2di (__a);
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}
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__extension__ static __inline uint8_t __attribute__ ((__always_inline__))
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vaddvq_u8 (uint8x16_t __a)
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{
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return vgetq_lane_u8 ((uint8x16_t)
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__builtin_aarch64_reduc_uplus_v16qi ((int8x16_t) __a),
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0);
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return (uint8_t) __builtin_aarch64_reduc_plus_scal_v16qi ((int8x16_t) __a);
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}
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__extension__ static __inline uint16_t __attribute__ ((__always_inline__))
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vaddvq_u16 (uint16x8_t __a)
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{
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return vgetq_lane_u16 ((uint16x8_t)
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__builtin_aarch64_reduc_uplus_v8hi ((int16x8_t) __a),
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0);
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return (uint16_t) __builtin_aarch64_reduc_plus_scal_v8hi ((int16x8_t) __a);
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}
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__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
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vaddvq_u32 (uint32x4_t __a)
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{
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return vgetq_lane_u32 ((uint32x4_t)
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__builtin_aarch64_reduc_uplus_v4si ((int32x4_t) __a),
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0);
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return (uint32_t) __builtin_aarch64_reduc_plus_scal_v4si ((int32x4_t) __a);
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}
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__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
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vaddvq_u64 (uint64x2_t __a)
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{
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return vgetq_lane_u64 ((uint64x2_t)
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__builtin_aarch64_reduc_uplus_v2di ((int64x2_t) __a),
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0);
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return (uint64_t) __builtin_aarch64_reduc_plus_scal_v2di ((int64x2_t) __a);
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}
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__extension__ static __inline float32_t __attribute__ ((__always_inline__))
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vaddv_f32 (float32x2_t __a)
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{
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float32x2_t __t = __builtin_aarch64_reduc_splus_v2sf (__a);
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return vget_lane_f32 (__t, 0);
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return __builtin_aarch64_reduc_plus_scal_v2sf (__a);
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}
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__extension__ static __inline float32_t __attribute__ ((__always_inline__))
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vaddvq_f32 (float32x4_t __a)
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{
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float32x4_t __t = __builtin_aarch64_reduc_splus_v4sf (__a);
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return vgetq_lane_f32 (__t, 0);
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return __builtin_aarch64_reduc_plus_scal_v4sf (__a);
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}
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__extension__ static __inline float64_t __attribute__ ((__always_inline__))
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vaddvq_f64 (float64x2_t __a)
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{
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float64x2_t __t = __builtin_aarch64_reduc_splus_v2df (__a);
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return vgetq_lane_f64 (__t, 0);
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return __builtin_aarch64_reduc_plus_scal_v2df (__a);
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}
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/* vbsl */
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@ -19777,7 +19759,7 @@ vpadd_u32 (uint32x2_t __a, uint32x2_t __b)
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__extension__ static __inline float64_t __attribute__ ((__always_inline__))
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vpaddd_f64 (float64x2_t __a)
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{
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return vgetq_lane_f64 (__builtin_aarch64_reduc_splus_v2df (__a), 0);
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return __builtin_aarch64_reduc_plus_scal_v2df (__a);
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}
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__extension__ static __inline int64_t __attribute__ ((__always_inline__))
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@ -213,8 +213,7 @@
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UNSPEC_FMINNMV ; Used in aarch64-simd.md.
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UNSPEC_FMINV ; Used in aarch64-simd.md.
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UNSPEC_FADDV ; Used in aarch64-simd.md.
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UNSPEC_SADDV ; Used in aarch64-simd.md.
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UNSPEC_UADDV ; Used in aarch64-simd.md.
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UNSPEC_ADDV ; Used in aarch64-simd.md.
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UNSPEC_SMAXV ; Used in aarch64-simd.md.
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UNSPEC_SMINV ; Used in aarch64-simd.md.
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UNSPEC_UMAXV ; Used in aarch64-simd.md.
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@ -859,8 +858,6 @@
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(define_int_iterator FMAXMINV [UNSPEC_FMAXV UNSPEC_FMINV
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UNSPEC_FMAXNMV UNSPEC_FMINNMV])
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(define_int_iterator SUADDV [UNSPEC_SADDV UNSPEC_UADDV])
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(define_int_iterator HADDSUB [UNSPEC_SHADD UNSPEC_UHADD
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UNSPEC_SRHADD UNSPEC_URHADD
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UNSPEC_SHSUB UNSPEC_UHSUB
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@ -965,7 +962,6 @@
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(UNSPEC_SUBHN2 "") (UNSPEC_RSUBHN2 "r")
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(UNSPEC_SQXTN "s") (UNSPEC_UQXTN "u")
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(UNSPEC_USQADD "us") (UNSPEC_SUQADD "su")
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(UNSPEC_SADDV "s") (UNSPEC_UADDV "u")
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(UNSPEC_SSLI "s") (UNSPEC_USLI "u")
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(UNSPEC_SSRI "s") (UNSPEC_USRI "u")
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(UNSPEC_USRA "u") (UNSPEC_SSRA "s")
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