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RISC-V: Add vector registers in TARGET_CONDITIONAL_REGISTER_USAGE

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gcc/ChangeLog:

	* config/riscv/riscv.cc (riscv_conditional_register_usage): Add vector
	registers.
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zhongjuzhe 2022-08-30 14:27:52 +08:00 • committed by Kito Cheng
parent 8fe75147a9
commit e8c83ab9d5
1 changed files with 9 additions and 0 deletions
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9
gcc/config/riscv/riscv.cc
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@ -5438,6 +5438,15 @@ riscv_conditional_register_usage (void)
for (int regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++)
call_used_regs[regno] = 1;
}
if (!TARGET_VECTOR)
{
for (int regno = V_REG_FIRST; regno <= V_REG_LAST; regno++)
fixed_regs[regno] = call_used_regs[regno] = 1;
fixed_regs[VTYPE_REGNUM] = call_used_regs[VTYPE_REGNUM] = 1;
fixed_regs[VL_REGNUM] = call_used_regs[VL_REGNUM] = 1;
}
}
/* Return a register priority for hard reg REGNO. */