RISC-V: Add csrr vlenb instruction.
gcc/ChangeLog: * config/riscv/riscv.cc (riscv_const_insns): Add cost of poly_int. (riscv_output_move): Add csrr vlenb assembly. * config/riscv/riscv.md (move_type): Add csrr vlenb type. (ext): New attribute. (ext_enabled): Ditto. (enabled): Ditto.
This commit is contained in:
zhongjuzhe
Kito Cheng
parent
e8089aff36
commit
8fe75147a9
2 changed files with 69 additions and 22 deletions
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@ -1136,6 +1136,12 @@ riscv_const_insns (rtx x)
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case LABEL_REF:
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return riscv_symbol_insns (riscv_classify_symbol (x));
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/* TODO: In RVV, we get CONST_POLY_INT by using csrr VLENB
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instruction and several scalar shift or mult instructions,
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it is so far unknown. We set it to 4 temporarily. */
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case CONST_POLY_INT:
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return 4;
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default:
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return 0;
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}
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@ -2507,6 +2513,12 @@ riscv_output_move (rtx dest, rtx src)
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return "fld\t%0,%1";
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}
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}
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if (dest_code == REG && GP_REG_P (REGNO (dest)) && src_code == CONST_POLY_INT)
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{
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/* We only want a single full vector register VLEN read after reload. */
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gcc_assert (known_eq (rtx_to_poly_int64 (src), BYTES_PER_RISCV_VECTOR));
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return "csrr\t%0,vlenb";
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}
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gcc_unreachable ();
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}
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@ -148,7 +148,7 @@
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;; scheduling type to be "multi" instead.
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(define_attr "move_type"
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"unknown,load,fpload,store,fpstore,mtc,mfc,move,fmove,
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const,logical,arith,andi,shift_shift"
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const,logical,arith,andi,shift_shift,rdvlenb"
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(const_string "unknown"))
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;; Main data type used by the insn
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@ -166,6 +166,35 @@
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(const_string "yes")]
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(const_string "no")))
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;; ISA attributes.
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(define_attr "ext" "base,f,d,vector"
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(const_string "base"))
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;; True if the extension is enabled.
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(define_attr "ext_enabled" "no,yes"
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(cond [(eq_attr "ext" "base")
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(const_string "yes")
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(and (eq_attr "ext" "f")
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(match_test "TARGET_HARD_FLOAT"))
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(const_string "yes")
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(and (eq_attr "ext" "d")
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(match_test "TARGET_DOUBLE_FLOAT"))
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(const_string "yes")
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(and (eq_attr "ext" "vector")
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(match_test "TARGET_VECTOR"))
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(const_string "yes")
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]
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(const_string "no")))
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;; Attribute to control enable or disable instructions.
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(define_attr "enabled" "no,yes"
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(cond [(eq_attr "ext_enabled" "no")
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(const_string "no")]
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(const_string "yes")))
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;; Classification of each insn.
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;; branch conditional branch
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;; jump unconditional jump
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@ -326,7 +355,8 @@
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(eq_attr "dword_mode" "yes"))
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(const_string "multi")
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(eq_attr "move_type" "move") (const_string "move")
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(eq_attr "move_type" "const") (const_string "const")]
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(eq_attr "move_type" "const") (const_string "const")
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(eq_attr "move_type" "rdvlenb") (const_string "rdvlenb")]
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(const_string "unknown")))
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;; Length of instruction in bytes.
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@ -1633,24 +1663,26 @@
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})
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(define_insn "*movdi_32bit"
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[(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,m, *f,*f,*r,*f,*m")
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(match_operand:DI 1 "move_operand" " r,i,m,r,*J*r,*m,*f,*f,*f"))]
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[(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,m, *f,*f,*r,*f,*m,r")
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(match_operand:DI 1 "move_operand" " r,i,m,r,*J*r,*m,*f,*f,*f,vp"))]
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"!TARGET_64BIT
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&& (register_operand (operands[0], DImode)
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|| reg_or_0_operand (operands[1], DImode))"
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{ return riscv_output_move (operands[0], operands[1]); }
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[(set_attr "move_type" "move,const,load,store,mtc,fpload,mfc,fmove,fpstore")
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(set_attr "mode" "DI")])
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[(set_attr "move_type" "move,const,load,store,mtc,fpload,mfc,fmove,fpstore,rdvlenb")
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(set_attr "mode" "DI")
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(set_attr "ext" "base,base,base,base,d,d,d,d,d,vector")])
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(define_insn "*movdi_64bit"
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[(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r, m, *f,*f,*r,*f,*m")
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(match_operand:DI 1 "move_operand" " r,T,m,rJ,*r*J,*m,*f,*f,*f"))]
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[(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r, m, *f,*f,*r,*f,*m,r")
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(match_operand:DI 1 "move_operand" " r,T,m,rJ,*r*J,*m,*f,*f,*f,vp"))]
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"TARGET_64BIT
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&& (register_operand (operands[0], DImode)
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|| reg_or_0_operand (operands[1], DImode))"
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{ return riscv_output_move (operands[0], operands[1]); }
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[(set_attr "move_type" "move,const,load,store,mtc,fpload,mfc,fmove,fpstore")
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(set_attr "mode" "DI")])
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[(set_attr "move_type" "move,const,load,store,mtc,fpload,mfc,fmove,fpstore,rdvlenb")
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(set_attr "mode" "DI")
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(set_attr "ext" "base,base,base,base,d,d,d,d,d,vector")])
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;; 32-bit Integer moves
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@ -1664,13 +1696,14 @@
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})
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(define_insn "*movsi_internal"
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[(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r, m, *f,*f,*r,*m")
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(match_operand:SI 1 "move_operand" " r,T,m,rJ,*r*J,*m,*f,*f"))]
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[(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r, m, *f,*f,*r,*m,r")
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(match_operand:SI 1 "move_operand" " r,T,m,rJ,*r*J,*m,*f,*f,vp"))]
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"(register_operand (operands[0], SImode)
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|| reg_or_0_operand (operands[1], SImode))"
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{ return riscv_output_move (operands[0], operands[1]); }
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[(set_attr "move_type" "move,const,load,store,mtc,fpload,mfc,fpstore")
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(set_attr "mode" "SI")])
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[(set_attr "move_type" "move,const,load,store,mtc,fpload,mfc,fpstore,rdvlenb")
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(set_attr "mode" "SI")
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(set_attr "ext" "base,base,base,base,f,f,f,f,vector")])
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;; 16-bit Integer moves
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@ -1689,13 +1722,14 @@
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})
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(define_insn "*movhi_internal"
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[(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r, m, *f,*r")
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(match_operand:HI 1 "move_operand" " r,T,m,rJ,*r*J,*f"))]
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[(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r, m, *f,*r,r")
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(match_operand:HI 1 "move_operand" " r,T,m,rJ,*r*J,*f,vp"))]
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"(register_operand (operands[0], HImode)
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|| reg_or_0_operand (operands[1], HImode))"
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{ return riscv_output_move (operands[0], operands[1]); }
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[(set_attr "move_type" "move,const,load,store,mtc,mfc")
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(set_attr "mode" "HI")])
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[(set_attr "move_type" "move,const,load,store,mtc,mfc,rdvlenb")
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(set_attr "mode" "HI")
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(set_attr "ext" "base,base,base,base,f,f,vector")])
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;; HImode constant generation; see riscv_move_integer for details.
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;; si+si->hi without truncation is legal because of
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@ -1731,13 +1765,14 @@
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})
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(define_insn "*movqi_internal"
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[(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r, m, *f,*r")
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(match_operand:QI 1 "move_operand" " r,I,m,rJ,*r*J,*f"))]
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[(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r, m, *f,*r,r")
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(match_operand:QI 1 "move_operand" " r,I,m,rJ,*r*J,*f,vp"))]
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"(register_operand (operands[0], QImode)
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|| reg_or_0_operand (operands[1], QImode))"
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{ return riscv_output_move (operands[0], operands[1]); }
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[(set_attr "move_type" "move,const,load,store,mtc,mfc")
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(set_attr "mode" "QI")])
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[(set_attr "move_type" "move,const,load,store,mtc,mfc,rdvlenb")
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(set_attr "mode" "QI")
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(set_attr "ext" "base,base,base,base,f,f,vector")])
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;; 32-bit floating point moves
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