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RISC-V: Add RVV constraints.

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gcc/ChangeLog:

	* config/riscv/constraints.md (TARGET_VECTOR ? V_REGS : NO_REGS): Add
	"vr" constraint.
	(TARGET_VECTOR ? VD_REGS : NO_REGS): Add "vd" constraint.
	(TARGET_VECTOR ? VM_REGS : NO_REGS): Add "vm" constraint.
	(vp): Add poly constraint.
This commit is contained in:
zhongjuzhe 2022-08-30 14:13:51 +08:00 • committed by Kito Cheng
parent 45f1287268
commit e8089aff36
1 changed files with 20 additions and 0 deletions
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20
gcc/config/riscv/constraints.md
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@ -108,3 +108,23 @@
A constant @code{move_operand}."
(and (match_operand 0 "move_operand")
(match_test "CONSTANT_P (op)")))
;; Vector constraints.
(define_register_constraint "vr" "TARGET_VECTOR ? V_REGS : NO_REGS"
"A vector register (if available).")
(define_register_constraint "vd" "TARGET_VECTOR ? VD_REGS : NO_REGS"
"A vector register except mask register (if available).")
(define_register_constraint "vm" "TARGET_VECTOR ? VM_REGS : NO_REGS"
"A vector mask register (if available).")
;; This constraint is used to match instruction "csrr %0, vlenb" which is generated in "mov<mode>".
;; VLENB is a run-time constant which represent the vector register length in bytes.
;; BYTES_PER_RISCV_VECTOR represent runtime invariant of vector register length in bytes.
;; We should only allow the poly equal to BYTES_PER_RISCV_VECTOR.
(define_constraint "vp"
"POLY_INT"
(and (match_code "const_poly_int")
(match_test "known_eq (rtx_to_poly_int64 (op), BYTES_PER_RISCV_VECTOR)")))