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testsuite: arm: Relax register selection [PR116623]

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Since r15-1619-g3b9b8d6cfdf, test5 and test8 fails due to that "ip"
might be used and r3 might be moved to another register for later
dereference.

gcc/testsuite/ChangeLog:

	PR testsuite/116623
	* gcc.target/arm/mve/dlstp-compile-asm-2.c: Align test5 and
	test8 with changes in r15-1619-g3b9b8d6cfdf.

Signed-off-by: Torbjörn SVENSSON <torbjorn.svensson@foss.st.com>
This commit is contained in:
Torbjörn SVENSSON 2024-10-19 18:08:01 +02:00
parent 4602f628f7
commit e152a73433
1 changed files with 6 additions and 4 deletions
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10
gcc/testsuite/gcc.target/arm/mve/dlstp-compile-asm-2.c
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@ -147,15 +147,17 @@ void test5 (uint8_t *a, uint8_t *b, uint8_t *c, uint8_t *d, int n)
/*
** test5:
**...
** dlstp.8 lr, r[0-9]+
** (?:mov (r[0-9]+), r3)?
**...
** dlstp.8 lr, (?:r[0-9]+|ip)
**...
** vldrb.8 q[0-9]+, \[r1\]
** vldrb.8 q[0-9]+, \[r2\]
**...
** vadd.i8 (q[0-9]+), q[0-9]+, q[0-9]+
**...
** vstrb.8 \1, \[r2\]
** vstrb.8 \1, \[r3\]
** vstrb.8 \2, \[r2\]
** vstrb.8 \2, \[(r3|\1)\]
** letp lr, .*
**...
*/
@ -247,7 +249,7 @@ void test8 (int32_t *a, int32_t *b, int32_t *c, int n, int g)
**...
** dlstp.32 lr, r3
** vldrw.32 q[0-9]+, \[r0\], #16
** vctp.32 r4
** vctp.32 (?:r4|ip)
** vpst
** vldrwt.32 q[0-9]+, \[r1\], #16
**...