From e152a734337a06ed085c2e6700f21cda9ca7ad17 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Torbj=C3=B6rn=20SVENSSON?= Date: Sat, 19 Oct 2024 18:08:01 +0200 Subject: [PATCH] testsuite: arm: Relax register selection [PR116623] MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Since r15-1619-g3b9b8d6cfdf, test5 and test8 fails due to that "ip" might be used and r3 might be moved to another register for later dereference. gcc/testsuite/ChangeLog: PR testsuite/116623 * gcc.target/arm/mve/dlstp-compile-asm-2.c: Align test5 and test8 with changes in r15-1619-g3b9b8d6cfdf. Signed-off-by: Torbjörn SVENSSON --- gcc/testsuite/gcc.target/arm/mve/dlstp-compile-asm-2.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/gcc/testsuite/gcc.target/arm/mve/dlstp-compile-asm-2.c b/gcc/testsuite/gcc.target/arm/mve/dlstp-compile-asm-2.c index 84f4a2fc4f9..c62f592a60d 100644 --- a/gcc/testsuite/gcc.target/arm/mve/dlstp-compile-asm-2.c +++ b/gcc/testsuite/gcc.target/arm/mve/dlstp-compile-asm-2.c @@ -147,15 +147,17 @@ void test5 (uint8_t *a, uint8_t *b, uint8_t *c, uint8_t *d, int n) /* ** test5: **... -** dlstp.8 lr, r[0-9]+ +** (?:mov (r[0-9]+), r3)? +**... +** dlstp.8 lr, (?:r[0-9]+|ip) **... ** vldrb.8 q[0-9]+, \[r1\] ** vldrb.8 q[0-9]+, \[r2\] **... ** vadd.i8 (q[0-9]+), q[0-9]+, q[0-9]+ **... -** vstrb.8 \1, \[r2\] -** vstrb.8 \1, \[r3\] +** vstrb.8 \2, \[r2\] +** vstrb.8 \2, \[(r3|\1)\] ** letp lr, .* **... */ @@ -247,7 +249,7 @@ void test8 (int32_t *a, int32_t *b, int32_t *c, int n, int g) **... ** dlstp.32 lr, r3 ** vldrw.32 q[0-9]+, \[r0\], #16 -** vctp.32 r4 +** vctp.32 (?:r4|ip) ** vpst ** vldrwt.32 q[0-9]+, \[r1\], #16 **...