LoongArch: Optimize for conditional move operations
The optimization example is as follows.
From:
if (condition)
dest += 1 << 16;
To:
dest += (condition ? 1 : 0) << 16;
It does not use maskeqz and masknez, thus reducing the number of
instructions.
gcc/ChangeLog:
* config/loongarch/loongarch.cc
(loongarch_expand_conditional_move): Add some optimization
implementations based on noce_try_cmove_arith.
gcc/testsuite/ChangeLog:
* gcc.target/loongarch/conditional-move-opt-1.c: New test.
* gcc.target/loongarch/conditional-move-opt-2.c: New test.
This commit is contained in:
Guo Jie
Lulu Cheng
parent
ea7476516d
commit
d55d40afd4
3 changed files with 202 additions and 1 deletions
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@ -5294,6 +5294,81 @@ loongarch_expand_conditional_move (rtx *operands)
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loongarch_emit_float_compare (&code, &op0, &op1);
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else
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{
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/* Optimize to reduce the number of instructions for ternary operations.
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Mainly implemented based on noce_try_cmove_arith.
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For dest = (condition) ? value_if_true : value_if_false;
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the optimization requires:
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a. value_if_false = var;
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b. value_if_true = var OP C (a positive integer power of 2).
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Situations similar to the following:
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if (condition)
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dest += 1 << imm;
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to:
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dest += (condition ? 1 : 0) << imm; */
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rtx_insn *insn;
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HOST_WIDE_INT val = 0; /* The value of rtx C. */
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/* INSN with operands[2] as the output. */
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rtx_insn *value_if_true_insn = NULL;
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/* INSN with operands[3] as the output. */
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rtx_insn *value_if_false_insn = NULL;
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rtx value_if_true_insn_src = NULL_RTX;
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/* Common operand var in value_if_true and value_if_false. */
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rtx comm_var = NULL_RTX;
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bool can_be_optimized = false;
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/* Search value_if_true_insn and value_if_false_insn. */
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struct sequence_stack *seq = get_current_sequence ()->next;
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for (insn = seq->last; insn; insn = PREV_INSN (insn))
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{
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if (single_set (insn))
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{
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rtx set_dest = SET_DEST (single_set (insn));
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if (rtx_equal_p (set_dest, operands[2]))
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value_if_true_insn = insn;
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else if (rtx_equal_p (set_dest, operands[3]))
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value_if_false_insn = insn;
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if (value_if_true_insn && value_if_false_insn)
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break;
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}
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}
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/* Check if the optimization conditions are met. */
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if (value_if_true_insn
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&& value_if_false_insn
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/* Make sure that value_if_false and var are the same. */
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&& BINARY_P (value_if_true_insn_src
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= SET_SRC (single_set (value_if_true_insn)))
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/* Make sure that both value_if_true and value_if_false
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has the same var. */
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&& rtx_equal_p (XEXP (value_if_true_insn_src, 0),
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SET_SRC (single_set (value_if_false_insn))))
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{
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comm_var = SET_SRC (single_set (value_if_false_insn));
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rtx src = XEXP (value_if_true_insn_src, 1);
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rtx imm = NULL_RTX;
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if (CONST_INT_P (src))
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imm = src;
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else
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for (insn = seq->last; insn; insn = PREV_INSN (insn))
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{
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rtx set = single_set (insn);
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if (set && rtx_equal_p (SET_DEST (set), src))
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{
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imm = SET_SRC (set);
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break;
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}
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}
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if (imm && CONST_INT_P (imm))
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{
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val = INTVAL (imm);
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/* Make sure that imm is a positive integer power of 2. */
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if (val > 0 && !(val & (val - 1)))
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can_be_optimized = true;
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}
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}
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if (GET_MODE_SIZE (GET_MODE (op0)) < UNITS_PER_WORD)
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{
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promote_op[0] = (REG_P (op0) && REG_P (operands[2]) &&
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@ -5314,22 +5389,48 @@ loongarch_expand_conditional_move (rtx *operands)
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op0_extend = op0;
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op1_extend = force_reg (word_mode, op1);
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rtx target = gen_reg_rtx (GET_MODE (op0));
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if (code == EQ || code == NE)
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{
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op0 = loongarch_zero_if_equal (op0, op1);
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op1 = const0_rtx;
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/* For EQ, set target to 1 if op0 and op1 are the same,
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otherwise set to 0.
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For NE, set target to 0 if op0 and op1 are the same,
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otherwise set to 1. */
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if (can_be_optimized)
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loongarch_emit_binary (code, target, op0, const0_rtx);
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}
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else
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{
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/* The comparison needs a separate scc instruction. Store the
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result of the scc in *OP0 and compare it against zero. */
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bool invert = false;
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rtx target = gen_reg_rtx (GET_MODE (op0));
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loongarch_emit_int_order_test (code, &invert, target, op0, op1);
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if (can_be_optimized && invert)
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loongarch_emit_binary (EQ, target, target, const0_rtx);
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code = invert ? EQ : NE;
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op0 = target;
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op1 = const0_rtx;
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}
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if (can_be_optimized)
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{
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/* Perform (condition ? 1 : 0) << log2 (C). */
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loongarch_emit_binary (ASHIFT, target, target,
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GEN_INT (exact_log2 (val)));
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/* Shift-related insn patterns only support SImode operands[2]. */
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enum rtx_code opcode = GET_CODE (value_if_true_insn_src);
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if (opcode == ASHIFT || opcode == ASHIFTRT || opcode == LSHIFTRT
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|| opcode == ROTATE || opcode == ROTATERT)
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target = gen_lowpart (SImode, target);
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/* Perform target = target OP ((condition ? 1 : 0) << log2 (C)). */
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loongarch_emit_binary (opcode, operands[0],
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force_reg (GET_MODE (operands[3]), comm_var),
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target);
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return;
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}
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}
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rtx cond = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1);
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58
gcc/testsuite/gcc.target/loongarch/conditional-move-opt-1.c
Normal file
58
gcc/testsuite/gcc.target/loongarch/conditional-move-opt-1.c
Normal file
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@ -0,0 +1,58 @@
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/* { dg-do compile } */
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/* { dg-options "-O2" } */
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/* { dg-final { scan-assembler-not "maskeqz" } } */
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/* { dg-final { scan-assembler-not "masknez" } } */
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extern long lm, ln, lr;
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void
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test_ne ()
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{
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if (lm != ln)
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lr += (1 << 16);
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lr += lm;
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}
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void
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test_eq ()
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{
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if (lm == ln)
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lr = lm + (1 << 16);
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else
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lr = lm;
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lr += lm;
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}
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void
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test_lt ()
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{
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if (lm < ln)
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lr *= (1 << 16);
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lr += lm;
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}
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void
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test_le ()
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{
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if (lm <= ln)
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lr = lm * ((long)1 << 32);
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else
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lr = lm;
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lr += lm;
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}
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void
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test_nez ()
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{
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if (lm != 0)
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lr <<= (1 << 4);
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lr += lm;
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}
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void
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test_eqz ()
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{
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if (lm == 0)
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lr >>= (1 << 2);
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lr += lm;
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}
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42
gcc/testsuite/gcc.target/loongarch/conditional-move-opt-2.c
Normal file
42
gcc/testsuite/gcc.target/loongarch/conditional-move-opt-2.c
Normal file
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@ -0,0 +1,42 @@
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/* { dg-do compile } */
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/* { dg-options "-O2 --param max-rtl-if-conversion-insns=1" } */
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/* { dg-final { scan-assembler-not "maskeqz" } } */
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/* { dg-final { scan-assembler-not "masknez" } } */
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/* The relevant optimization is currently only based on noce_try_cmove_arith,
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so it bypasses noce_convert_multiple_sets by
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--param max-rtl-if-conversion-insns=1 to execute noce_try_cmove_arith. */
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extern long lm, ln, lr;
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void
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test_ge ()
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{
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if (lm >= ln)
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lr += ((long)1 << 32);
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lr += lm;
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}
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void
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test_ltz ()
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{
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if (lm < 0)
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lr |= (1 << 16);
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lr += lm;
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}
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void
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test_lez ()
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{
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if (lm <= 0)
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lr &= (1 << 16);
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lr += lm;
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}
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void
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test_gez ()
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{
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if (lm >= 0)
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lr ^= (1 << 16);
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lr += lm;
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}
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