LoongArch: Add standard patterns uabd and sabd
gcc/ChangeLog: * config/loongarch/lasx.md (lasx_xvabsd_s_<lasxfmt>): Remove. (<su>abd<mode>3): New insn pattern. (lasx_xvabsd_u_<lasxfmt_u>): Remove. * config/loongarch/loongarch-builtins.cc (CODE_FOR_lsx_vabsd_b): Rename. (CODE_FOR_lsx_vabsd_h): Ditto. (CODE_FOR_lsx_vabsd_w): Ditto. (CODE_FOR_lsx_vabsd_d): Ditto. (CODE_FOR_lsx_vabsd_bu): Ditto. (CODE_FOR_lsx_vabsd_hu): Ditto. (CODE_FOR_lsx_vabsd_wu): Ditto. (CODE_FOR_lsx_vabsd_du): Ditto. (CODE_FOR_lasx_xvabsd_b): Ditto. (CODE_FOR_lasx_xvabsd_h): Ditto. (CODE_FOR_lasx_xvabsd_w): Ditto. (CODE_FOR_lasx_xvabsd_d): Ditto. (CODE_FOR_lasx_xvabsd_bu): Ditto. (CODE_FOR_lasx_xvabsd_hu): Ditto. (CODE_FOR_lasx_xvabsd_wu): Ditto. (CODE_FOR_lasx_xvabsd_du): Ditto. * config/loongarch/loongarch.md (u): Add smax/umax. * config/loongarch/lsx.md (SU_MAX): New iterator. (su_min): New attr. (lsx_vabsd_s_<lsxfmt>): Remove. (<su>abd<mode>3): New insn pattern. (lsx_vabsd_u_<lsxfmt_u>): Remove. gcc/testsuite/ChangeLog: * gcc.target/loongarch/abd-lasx.c: New test. * gcc.target/loongarch/abd-lsx.c: New test.
This commit is contained in:
Guo Jie
Lulu Cheng
parent
66a88e0f17
commit
ea7476516d
6 changed files with 181 additions and 56 deletions
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@ -20,8 +20,6 @@
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;;
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(define_c_enum "unspec" [
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UNSPEC_LASX_XVABSD_S
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UNSPEC_LASX_XVABSD_U
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UNSPEC_LASX_XVAVG_S
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UNSPEC_LASX_XVAVG_U
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UNSPEC_LASX_XVAVGR_S
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@ -1125,23 +1123,17 @@
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[(set_attr "type" "simd_int_arith")
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(set_attr "mode" "<MODE>")])
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(define_insn "lasx_xvabsd_s_<lasxfmt>"
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(define_insn "<su>abd<mode>3"
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[(set (match_operand:ILASX 0 "register_operand" "=f")
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(unspec:ILASX [(match_operand:ILASX 1 "register_operand" "f")
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(match_operand:ILASX 2 "register_operand" "f")]
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UNSPEC_LASX_XVABSD_S))]
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(minus:ILASX
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(SU_MAX:ILASX
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(match_operand:ILASX 1 "register_operand" "f")
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(match_operand:ILASX 2 "register_operand" "f"))
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(<su_min>:ILASX
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(match_dup 1)
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(match_dup 2))))]
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"ISA_HAS_LASX"
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"xvabsd.<lasxfmt>\t%u0,%u1,%u2"
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[(set_attr "type" "simd_int_arith")
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(set_attr "mode" "<MODE>")])
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(define_insn "lasx_xvabsd_u_<lasxfmt_u>"
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[(set (match_operand:ILASX 0 "register_operand" "=f")
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(unspec:ILASX [(match_operand:ILASX 1 "register_operand" "f")
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(match_operand:ILASX 2 "register_operand" "f")]
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UNSPEC_LASX_XVABSD_U))]
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"ISA_HAS_LASX"
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"xvabsd.<lasxfmt_u>\t%u0,%u1,%u2"
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"xvabsd.<lasxfmt><u>\t%u0,%u1,%u2"
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[(set_attr "type" "simd_int_arith")
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(set_attr "mode" "<MODE>")])
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@ -4926,7 +4918,7 @@
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rtx t1 = gen_reg_rtx (V32QImode);
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rtx t2 = gen_reg_rtx (V16HImode);
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rtx t3 = gen_reg_rtx (V8SImode);
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emit_insn (gen_lasx_xvabsd_u_bu (t1, operands[1], operands[2]));
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emit_insn (gen_uabdv32qi3 (t1, operands[1], operands[2]));
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emit_insn (gen_lasx_xvhaddw_hu_bu (t2, t1, t1));
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emit_insn (gen_lasx_xvhaddw_wu_hu (t3, t2, t2));
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emit_insn (gen_addv8si3 (operands[0], t3, operands[3]));
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@ -4943,7 +4935,7 @@
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rtx t1 = gen_reg_rtx (V32QImode);
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rtx t2 = gen_reg_rtx (V16HImode);
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rtx t3 = gen_reg_rtx (V8SImode);
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emit_insn (gen_lasx_xvabsd_s_b (t1, operands[1], operands[2]));
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emit_insn (gen_sabdv32qi3 (t1, operands[1], operands[2]));
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emit_insn (gen_lasx_xvhaddw_hu_bu (t2, t1, t1));
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emit_insn (gen_lasx_xvhaddw_wu_hu (t3, t2, t2));
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emit_insn (gen_addv8si3 (operands[0], t3, operands[3]));
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@ -462,14 +462,14 @@ AVAIL_ALL (lasx_frecipe, ISA_HAS_LASX && ISA_HAS_FRECIPE)
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#define CODE_FOR_lsx_vssub_hu CODE_FOR_lsx_vssub_u_hu
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#define CODE_FOR_lsx_vssub_wu CODE_FOR_lsx_vssub_u_wu
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#define CODE_FOR_lsx_vssub_du CODE_FOR_lsx_vssub_u_du
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#define CODE_FOR_lsx_vabsd_b CODE_FOR_lsx_vabsd_s_b
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#define CODE_FOR_lsx_vabsd_h CODE_FOR_lsx_vabsd_s_h
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#define CODE_FOR_lsx_vabsd_w CODE_FOR_lsx_vabsd_s_w
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#define CODE_FOR_lsx_vabsd_d CODE_FOR_lsx_vabsd_s_d
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#define CODE_FOR_lsx_vabsd_bu CODE_FOR_lsx_vabsd_u_bu
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#define CODE_FOR_lsx_vabsd_hu CODE_FOR_lsx_vabsd_u_hu
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#define CODE_FOR_lsx_vabsd_wu CODE_FOR_lsx_vabsd_u_wu
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#define CODE_FOR_lsx_vabsd_du CODE_FOR_lsx_vabsd_u_du
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#define CODE_FOR_lsx_vabsd_b CODE_FOR_sabdv16qi3
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#define CODE_FOR_lsx_vabsd_h CODE_FOR_sabdv8hi3
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#define CODE_FOR_lsx_vabsd_w CODE_FOR_sabdv4si3
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#define CODE_FOR_lsx_vabsd_d CODE_FOR_sabdv2di3
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#define CODE_FOR_lsx_vabsd_bu CODE_FOR_uabdv16qi3
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#define CODE_FOR_lsx_vabsd_hu CODE_FOR_uabdv8hi3
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#define CODE_FOR_lsx_vabsd_wu CODE_FOR_uabdv4si3
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#define CODE_FOR_lsx_vabsd_du CODE_FOR_uabdv2di3
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#define CODE_FOR_lsx_vftint_wu_s CODE_FOR_lsx_vftint_u_wu_s
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#define CODE_FOR_lsx_vftint_lu_d CODE_FOR_lsx_vftint_u_lu_d
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#define CODE_FOR_lsx_vandn_v CODE_FOR_andnv16qi3
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@ -742,14 +742,14 @@ AVAIL_ALL (lasx_frecipe, ISA_HAS_LASX && ISA_HAS_FRECIPE)
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#define CODE_FOR_lasx_xvssub_hu CODE_FOR_lasx_xvssub_u_hu
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#define CODE_FOR_lasx_xvssub_wu CODE_FOR_lasx_xvssub_u_wu
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#define CODE_FOR_lasx_xvssub_du CODE_FOR_lasx_xvssub_u_du
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#define CODE_FOR_lasx_xvabsd_b CODE_FOR_lasx_xvabsd_s_b
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#define CODE_FOR_lasx_xvabsd_h CODE_FOR_lasx_xvabsd_s_h
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#define CODE_FOR_lasx_xvabsd_w CODE_FOR_lasx_xvabsd_s_w
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#define CODE_FOR_lasx_xvabsd_d CODE_FOR_lasx_xvabsd_s_d
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#define CODE_FOR_lasx_xvabsd_bu CODE_FOR_lasx_xvabsd_u_bu
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#define CODE_FOR_lasx_xvabsd_hu CODE_FOR_lasx_xvabsd_u_hu
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#define CODE_FOR_lasx_xvabsd_wu CODE_FOR_lasx_xvabsd_u_wu
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#define CODE_FOR_lasx_xvabsd_du CODE_FOR_lasx_xvabsd_u_du
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#define CODE_FOR_lasx_xvabsd_b CODE_FOR_sabdv32qi3
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#define CODE_FOR_lasx_xvabsd_h CODE_FOR_sabdv16hi3
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#define CODE_FOR_lasx_xvabsd_w CODE_FOR_sabdv8si3
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#define CODE_FOR_lasx_xvabsd_d CODE_FOR_sabdv4di3
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#define CODE_FOR_lasx_xvabsd_bu CODE_FOR_uabdv32qi3
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#define CODE_FOR_lasx_xvabsd_hu CODE_FOR_uabdv16hi3
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#define CODE_FOR_lasx_xvabsd_wu CODE_FOR_uabdv8si3
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#define CODE_FOR_lasx_xvabsd_du CODE_FOR_uabdv4di3
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#define CODE_FOR_lasx_xvavg_b CODE_FOR_lasx_xvavg_s_b
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#define CODE_FOR_lasx_xvavg_h CODE_FOR_lasx_xvavg_s_h
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#define CODE_FOR_lasx_xvavg_w CODE_FOR_lasx_xvavg_s_w
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@ -527,13 +527,15 @@
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(gt "") (gtu "u")
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(ge "") (geu "u")
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(lt "") (ltu "u")
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(le "") (leu "u")])
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(le "") (leu "u")
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(smax "") (umax "u")])
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;; <U> is like <u> except uppercase.
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(define_code_attr U [(sign_extend "") (zero_extend "U")])
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;; <su> is like <u>, but the signed form expands to "s" rather than "".
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(define_code_attr su [(sign_extend "s") (zero_extend "u")])
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(define_code_attr su [(sign_extend "s") (zero_extend "u")
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(smax "s") (umax "u")])
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(define_code_attr u_bool [(sign_extend "false") (zero_extend "true")])
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@ -20,8 +20,6 @@
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;;
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(define_c_enum "unspec" [
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UNSPEC_LSX_ABSD_S
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UNSPEC_LSX_VABSD_U
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UNSPEC_LSX_VAVG_S
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UNSPEC_LSX_VAVG_U
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UNSPEC_LSX_VAVGR_S
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@ -191,6 +189,11 @@
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(V4SI "V8HI")
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(V2DI "V4SI")])
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;; Signed and unsigned max operations.
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(define_code_iterator SU_MAX [smax umax])
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(define_code_attr su_min [(smax "smin") (umax "umin")])
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;; The attribute gives double modes for vector modes.
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(define_mode_attr VDMODE
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[(V2DI "V2DI")
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@ -976,23 +979,17 @@
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[(set_attr "type" "simd_int_arith")
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(set_attr "mode" "<MODE>")])
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(define_insn "lsx_vabsd_s_<lsxfmt>"
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(define_insn "<su>abd<mode>3"
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[(set (match_operand:ILSX 0 "register_operand" "=f")
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(unspec:ILSX [(match_operand:ILSX 1 "register_operand" "f")
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(match_operand:ILSX 2 "register_operand" "f")]
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UNSPEC_LSX_ABSD_S))]
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(minus:ILSX
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(SU_MAX:ILSX
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(match_operand:ILSX 1 "register_operand" "f")
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(match_operand:ILSX 2 "register_operand" "f"))
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(<su_min>:ILSX
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(match_dup 1)
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(match_dup 2))))]
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"ISA_HAS_LSX"
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"vabsd.<lsxfmt>\t%w0,%w1,%w2"
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[(set_attr "type" "simd_int_arith")
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(set_attr "mode" "<MODE>")])
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(define_insn "lsx_vabsd_u_<lsxfmt_u>"
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[(set (match_operand:ILSX 0 "register_operand" "=f")
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(unspec:ILSX [(match_operand:ILSX 1 "register_operand" "f")
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(match_operand:ILSX 2 "register_operand" "f")]
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UNSPEC_LSX_VABSD_U))]
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"ISA_HAS_LSX"
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"vabsd.<lsxfmt_u>\t%w0,%w1,%w2"
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"vabsd.<lsxfmt><u>\t%w0,%w1,%w2"
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[(set_attr "type" "simd_int_arith")
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(set_attr "mode" "<MODE>")])
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@ -3181,7 +3178,7 @@
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rtx t1 = gen_reg_rtx (V16QImode);
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rtx t2 = gen_reg_rtx (V8HImode);
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rtx t3 = gen_reg_rtx (V4SImode);
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emit_insn (gen_lsx_vabsd_u_bu (t1, operands[1], operands[2]));
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emit_insn (gen_uabdv16qi3 (t1, operands[1], operands[2]));
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emit_insn (gen_lsx_vhaddw_hu_bu (t2, t1, t1));
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emit_insn (gen_lsx_vhaddw_wu_hu (t3, t2, t2));
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emit_insn (gen_addv4si3 (operands[0], t3, operands[3]));
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@ -3198,7 +3195,7 @@
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rtx t1 = gen_reg_rtx (V16QImode);
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rtx t2 = gen_reg_rtx (V8HImode);
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rtx t3 = gen_reg_rtx (V4SImode);
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emit_insn (gen_lsx_vabsd_s_b (t1, operands[1], operands[2]));
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emit_insn (gen_sabdv16qi3 (t1, operands[1], operands[2]));
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emit_insn (gen_lsx_vhaddw_hu_bu (t2, t1, t1));
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emit_insn (gen_lsx_vhaddw_wu_hu (t3, t2, t2));
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emit_insn (gen_addv4si3 (operands[0], t3, operands[3]));
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67
gcc/testsuite/gcc.target/loongarch/abd-lasx.c
Normal file
67
gcc/testsuite/gcc.target/loongarch/abd-lasx.c
Normal file
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@ -0,0 +1,67 @@
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/* { dg-do compile } */
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/* { dg-options "-O3 -mlasx -fdump-rtl-expand-all" } */
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#define ABD(x, y) ((x - y > 0) ? (x - y) : -(x - y))
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#define MAX(x, y) ((x) > (y) ? (x) : (y))
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#define MIN(x, y) ((x) < (y) ? (x) : (y))
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#define N 1024
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#define FUNC1(T) \
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void \
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sabd1_##T (signed T *restrict a, signed T *restrict b, \
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signed T *restrict out) \
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{ \
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for (int i = 0; i < N; i++) \
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out[i] = ABD (a[i], b[i]); \
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} \
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\
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void \
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uabd1_##T (unsigned T *restrict a, unsigned T *restrict b, \
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unsigned T *restrict out) \
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{ \
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for (int i = 0; i < N; i++) \
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out[i] = ABD (a[i], b[i]); \
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}
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#define FUNC2(T) \
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void \
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sabd2_##T (signed T *restrict a, signed T *restrict b, \
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signed T *restrict out) \
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{ \
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for (int i = 0; i < N; i++) \
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out[i] = MAX (a[i], b[i]) - MIN (a[i], b[i]); \
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} \
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\
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void \
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uabd2_##T (unsigned T *restrict a, unsigned T *restrict b, \
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unsigned T *restrict out) \
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{ \
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for (int i = 0; i < N; i++) \
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out[i] = MAX (a[i], b[i]) - MIN (a[i], b[i]); \
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}
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/* Verify if the expand pass fits standard pattern name. */
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FUNC1 (char)
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FUNC1 (short)
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FUNC1 (int)
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FUNC1 (long)
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/* Verify if the combiner works well. */
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FUNC2 (char)
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FUNC2 (short)
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FUNC2 (int)
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FUNC2 (long)
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/* { dg-final { scan-rtl-dump "Function sabd1_char.*ABD.*Function uabd1_char" "expand" } } */
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/* { dg-final { scan-rtl-dump "Function uabd1_char.*ABD.*Function sabd1_short" "expand" } } */
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/* { dg-final { scan-rtl-dump "Function sabd1_short.*ABD.*Function uabd1_short" "expand" } } */
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/* { dg-final { scan-rtl-dump "Function uabd1_short.*ABD.*Function sabd1_int" "expand" } } */
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/* { dg-final { scan-rtl-dump "Function sabd1_int.*ABD.*Function uabd1_int" "expand" } } */
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/* { dg-final { scan-rtl-dump "Function sabd1_long.*ABD.*Function uabd1_long" "expand" } } */
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/* { dg-final { scan-assembler-times "sabd2_char:.*\txvabsd\\.b.*-sabd2_char" 1 } } */
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/* { dg-final { scan-assembler-times "uabd2_char:.*\txvabsd\\.bu.*-uabd2_char" 1 } } */
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/* { dg-final { scan-assembler-times "sabd2_short:.*\txvabsd\\.h.*-sabd2_short" 1 } } */
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/* { dg-final { scan-assembler-times "uabd2_short:.*\txvabsd\\.hu.*-uabd2_short" 1 } } */
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/* { dg-final { scan-assembler-times "sabd2_int:.*\txvabsd\\.w.*-sabd2_int" 1 } } */
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/* { dg-final { scan-assembler-times "uabd2_int:.*\txvabsd\\.wu.*-uabd2_int" 1 } } */
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/* { dg-final { scan-assembler-times "sabd2_long:.*\txvabsd\\.d.*-sabd2_long" 1 } } */
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/* { dg-final { scan-assembler-times "uabd2_long:.*\txvabsd\\.du.*-uabd2_long" 1 } } */
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67
gcc/testsuite/gcc.target/loongarch/abd-lsx.c
Normal file
67
gcc/testsuite/gcc.target/loongarch/abd-lsx.c
Normal file
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@ -0,0 +1,67 @@
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/* { dg-do compile } */
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/* { dg-options "-O3 -mlsx -fdump-rtl-expand-all" } */
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#define ABD(x, y) ((x - y > 0) ? (x - y) : -(x - y))
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#define MAX(x, y) ((x) > (y) ? (x) : (y))
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#define MIN(x, y) ((x) < (y) ? (x) : (y))
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#define N 1024
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#define FUNC1(T) \
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void \
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sabd1_##T (signed T *restrict a, signed T *restrict b, \
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signed T *restrict out) \
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{ \
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for (int i = 0; i < N; i++) \
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out[i] = ABD (a[i], b[i]); \
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} \
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\
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void \
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uabd1_##T (unsigned T *restrict a, unsigned T *restrict b, \
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unsigned T *restrict out) \
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{ \
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for (int i = 0; i < N; i++) \
|
||||
out[i] = ABD (a[i], b[i]); \
|
||||
}
|
||||
|
||||
#define FUNC2(T) \
|
||||
void \
|
||||
sabd2_##T (signed T *restrict a, signed T *restrict b, \
|
||||
signed T *restrict out) \
|
||||
{ \
|
||||
for (int i = 0; i < N; i++) \
|
||||
out[i] = MAX (a[i], b[i]) - MIN (a[i], b[i]); \
|
||||
} \
|
||||
\
|
||||
void \
|
||||
uabd2_##T (unsigned T *restrict a, unsigned T *restrict b, \
|
||||
unsigned T *restrict out) \
|
||||
{ \
|
||||
for (int i = 0; i < N; i++) \
|
||||
out[i] = MAX (a[i], b[i]) - MIN (a[i], b[i]); \
|
||||
}
|
||||
|
||||
/* Verify if the expand pass fits standard pattern name. */
|
||||
FUNC1 (char)
|
||||
FUNC1 (short)
|
||||
FUNC1 (int)
|
||||
FUNC1 (long)
|
||||
|
||||
/* Verify if the combiner works well. */
|
||||
FUNC2 (char)
|
||||
FUNC2 (short)
|
||||
FUNC2 (int)
|
||||
FUNC2 (long)
|
||||
/* { dg-final { scan-rtl-dump "Function sabd1_char.*ABD.*Function uabd1_char" "expand" } } */
|
||||
/* { dg-final { scan-rtl-dump "Function uabd1_char.*ABD.*Function sabd1_short" "expand" } } */
|
||||
/* { dg-final { scan-rtl-dump "Function sabd1_short.*ABD.*Function uabd1_short" "expand" } } */
|
||||
/* { dg-final { scan-rtl-dump "Function uabd1_short.*ABD.*Function sabd1_int" "expand" } } */
|
||||
/* { dg-final { scan-rtl-dump "Function sabd1_int.*ABD.*Function uabd1_int" "expand" } } */
|
||||
/* { dg-final { scan-rtl-dump "Function sabd1_long.*ABD.*Function uabd1_long" "expand" } } */
|
||||
/* { dg-final { scan-assembler-times "sabd2_char:.*\tvabsd\\.b.*-sabd2_char" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "uabd2_char:.*\tvabsd\\.bu.*-uabd2_char" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "sabd2_short:.*\tvabsd\\.h.*-sabd2_short" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "uabd2_short:.*\tvabsd\\.hu.*-uabd2_short" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "sabd2_int:.*\tvabsd\\.w.*-sabd2_int" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "uabd2_int:.*\tvabsd\\.wu.*-uabd2_int" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "sabd2_long:.*\tvabsd\\.d.*-sabd2_long" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "uabd2_long:.*\tvabsd\\.du.*-uabd2_long" 1 } } */
|
||||
Loading…
Add table
Reference in a new issue