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RISC-V: Remove unnecessary vread_csr/vwrite_csr intrinsic.

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According to below RVV doc, the related intrinsic is not longer needed.

https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/249

Signed-off-by: Pan Li <pan2.li@intel.com>

gcc/ChangeLog:

	* config/riscv/riscv_vector.h (enum RVV_CSR): Removed.
	(vread_csr): Ditto.
	(vwrite_csr): Ditto.
This commit is contained in:
Pan Li 2023-07-27 10:34:57 +08:00
parent cdc6545833
commit d0ae71c26a
1 changed files with 0 additions and 51 deletions
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51
gcc/config/riscv/riscv_vector.h
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@ -35,57 +35,6 @@
extern "C" {
#endif
enum RVV_CSR {
RVV_VSTART = 0,
RVV_VXSAT,
RVV_VXRM,
RVV_VCSR,
};
__extension__ extern __inline unsigned long
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vread_csr(enum RVV_CSR csr)
{
unsigned long rv = 0;
switch (csr)
{
case RVV_VSTART:
__asm__ __volatile__ ("csrr\t%0,vstart" : "=r"(rv) : : "memory");
break;
case RVV_VXSAT:
__asm__ __volatile__ ("csrr\t%0,vxsat" : "=r"(rv) : : "memory");
break;
case RVV_VXRM:
__asm__ __volatile__ ("csrr\t%0,vxrm" : "=r"(rv) : : "memory");
break;
case RVV_VCSR:
__asm__ __volatile__ ("csrr\t%0,vcsr" : "=r"(rv) : : "memory");
break;
}
return rv;
}
__extension__ extern __inline void
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vwrite_csr(enum RVV_CSR csr, unsigned long value)
{
switch (csr)
{
case RVV_VSTART:
__asm__ __volatile__ ("csrw\tvstart,%z0" : : "rJ"(value) : "memory");
break;
case RVV_VXSAT:
__asm__ __volatile__ ("csrw\tvxsat,%z0" : : "rJ"(value) : "memory");
break;
case RVV_VXRM:
__asm__ __volatile__ ("csrw\tvxrm,%z0" : : "rJ"(value) : "memory");
break;
case RVV_VCSR:
__asm__ __volatile__ ("csrw\tvcsr,%z0" : : "rJ"(value) : "memory");
break;
}
}
/* NOTE: This implementation of riscv_vector.h is intentionally short. It does
not define the RVV types and intrinsic functions directly in C and C++
code, but instead uses the following pragma to tell GCC to insert the