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RISC-V: Fix uninitialized and redundant use of which_alternative

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When pass split2 starts, which_alternative is random depending on
last set of certain pass.

Even initialized, the generated movement is redundant.
The movement can be generated by assembly output template.

Signed-off-by: demin.han <demin.han@starfivetech.com>

gcc/ChangeLog:

	* config/riscv/autovec.md: Delete which_alternative use in split

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/madd-split2-1.c: New test.
Signed-off-by: demin.han <demin.han@starfivetech.com>
This commit is contained in:
demin.han 2023-07-27 17:48:59 +08:00 • committed by Kito Cheng
parent 41482832ad
commit cdc6545833
2 changed files with 13 additions and 12 deletions
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12
gcc/config/riscv/autovec.md
View file

@ -1012,8 +1012,6 @@
[(const_int 0)]
{
riscv_vector::emit_vlmax_vsetvl (<VI:MODE>mode, operands[4]);
if (which_alternative == 2)
emit_insn (gen_rtx_SET (operands[0], operands[3]));
rtx ops[] = {operands[0], operands[1], operands[2], operands[3], operands[0]};
riscv_vector::emit_vlmax_ternary_insn (code_for_pred_mul_plus (<VI:MODE>mode),
riscv_vector::RVV_TERNOP, ops, operands[4]);
@ -1058,8 +1056,6 @@
[(const_int 0)]
{
riscv_vector::emit_vlmax_vsetvl (<VI:MODE>mode, operands[4]);
if (which_alternative == 2)
emit_insn (gen_rtx_SET (operands[0], operands[3]));
rtx ops[] = {operands[0], operands[1], operands[2], operands[3], operands[0]};
riscv_vector::emit_vlmax_ternary_insn (code_for_pred_minus_mul (<VI:MODE>mode),
riscv_vector::RVV_TERNOP, ops, operands[4]);
@ -1102,8 +1098,6 @@
[(const_int 0)]
{
riscv_vector::emit_vlmax_vsetvl (<VF:MODE>mode, operands[4]);
if (which_alternative == 2)
emit_insn (gen_rtx_SET (operands[0], operands[3]));
rtx ops[] = {operands[0], operands[1], operands[2], operands[3], operands[0]};
riscv_vector::emit_vlmax_fp_ternary_insn (code_for_pred_mul (PLUS, <VF:MODE>mode),
riscv_vector::RVV_TERNOP, ops, operands[4]);
@ -1148,8 +1142,6 @@
[(const_int 0)]
{
riscv_vector::emit_vlmax_vsetvl (<VF:MODE>mode, operands[4]);
if (which_alternative == 2)
emit_insn (gen_rtx_SET (operands[0], operands[3]));
rtx ops[] = {operands[0], operands[1], operands[2], operands[3], operands[0]};
riscv_vector::emit_vlmax_fp_ternary_insn (code_for_pred_mul_neg (PLUS, <VF:MODE>mode),
riscv_vector::RVV_TERNOP, ops, operands[4]);
@ -1194,8 +1186,6 @@
[(const_int 0)]
{
riscv_vector::emit_vlmax_vsetvl (<VF:MODE>mode, operands[4]);
if (which_alternative == 2)
emit_insn (gen_rtx_SET (operands[0], operands[3]));
rtx ops[] = {operands[0], operands[1], operands[2], operands[3], operands[0]};
riscv_vector::emit_vlmax_fp_ternary_insn (code_for_pred_mul (MINUS, <VF:MODE>mode),
riscv_vector::RVV_TERNOP, ops, operands[4]);
@ -1242,8 +1232,6 @@
[(const_int 0)]
{
riscv_vector::emit_vlmax_vsetvl (<VF:MODE>mode, operands[4]);
if (which_alternative == 2)
emit_insn (gen_rtx_SET (operands[0], operands[3]));
rtx ops[] = {operands[0], operands[1], operands[2], operands[3], operands[0]};
riscv_vector::emit_vlmax_fp_ternary_insn (code_for_pred_mul_neg (MINUS, <VF:MODE>mode),
riscv_vector::RVV_TERNOP, ops, operands[4]);

13
gcc/testsuite/gcc.target/riscv/rvv/autovec/madd-split2-1.c Normal file
View file

@ -0,0 +1,13 @@
/* { dg-do compile } */
/* { dg-options "-march=rv64gcv_zvl256b -O3 -fno-cprop-registers -fno-dce --param riscv-autovec-preference=scalable" } */
long
foo (long *__restrict a, long *__restrict b, long n)
{
long i;
for (i = 0; i < n; ++i)
a[i] = b[i] + i * 8;
return a[1];
}
/* { dg-final { scan-assembler-times {\tvmv1r\.v} 1 } } */