re PR target/48237 (ICE: in final_scan_insn, at final.c:2651 with -fselective-scheduling2 -mtune=core2)
PR target/48237 * config/i386/i386.md (*movdf_internal_rex64): Do not split alternatives that can be handled with movq or movabsq insn. (*movdf_internal): Disable for !TARGET_64BIT. (*movdf_internal_nointeger): Ditto. * config/i386/i386.c (ix86_print_operand): Handle DFmode immediates. testsuite/ChangeLog: PR target/48237 * gcc.target/i386/pr48237.c: New test. From-SVN: r171391
This commit is contained in:
Uros Bizjak
parent
4569f85ec0
commit
c78dd519d3
5 changed files with 100 additions and 50 deletions
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@ -1,15 +1,22 @@
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2011-03-24 Uros Bizjak <ubizjak@gmail.com>
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PR target/48237
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* config/i386/i386.md (*movdf_internal_rex64): Do not split
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alternatives that can be handled with movq or movabsq insn.
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(*movdf_internal): Disable for !TARGET_64BIT.
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(*movdf_internal_nointeger): Ditto.
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* config/i386/i386.c (ix86_print_operand): Handle DFmode immediates.
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2011-03-24 Nathan Froyd <froydnj@codesourcery.com>
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* system.h (FUNCTION_ARG, FUNCTION_INCOMING_ARG): Poison.
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(FUNCTION_ARG_ADVANCE): Likewise.
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* tm.texi.in: Change references to them to hook references.
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* tm.texi: Regenerate.
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* targhooks.c (default_function_arg): Eliminate check for target
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macro.
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* targhooks.c (default_function_arg): Eliminate check for target macro.
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(default_function_incoming_arg): Likewise.
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(default_function_arg_advance): Likewise.
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* target.def (function_arg, function_incoming_arg): Change to
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DEFHOOK.
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* target.def (function_arg, function_incoming_arg): Change to DEFHOOK.
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(function_arg_advance): Likewise.
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* target-def.h: Eliminate FUNCTION_INCOMING_ARG check.
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@ -22,8 +29,7 @@
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2011-03-24 Diego Novillo <dnovillo@google.com>
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* lto-opts.c (input_data_block): Move to lto-streamer-in.c.
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* lto-streamer-in.c (input_string_internal): Add clarifying
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comments.
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* lto-streamer-in.c (input_string_internal): Add clarifying comments.
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(lto_input_data_block): Move from lto-opts.c. Make extern.
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Update all users.
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(lto_input_string): Rename from input_string. Make extern.
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@ -134,8 +140,7 @@
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2011-03-23 Richard Guenther <rguenther@suse.de>
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* tree-stdarg.c (va_list_counter_bump): Handle bumps via
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MEM_REF.
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* tree-stdarg.c (va_list_counter_bump): Handle bumps via MEM_REF.
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(check_va_list_escapes): Likewise.
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(check_all_va_list_escapes): Likewise.
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@ -332,10 +337,8 @@
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(v850_handle_option): Access target_flags via opts pointer. Don't
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assert that global structures are in use. Update calls to
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v850_handle_memory_option.
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(v850_encode_data_area): Update references to small memory
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settings.
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* config/v850/v850.h (struct small_memory_info, small_memory):
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Remove.
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(v850_encode_data_area): Update references to small memory settings.
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* config/v850/v850.h (struct small_memory_info, small_memory): Remove.
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(enum small_memory_type): Move to v850-opts.h.
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* config/v850/v850.opt (config/v850/v850-opts.h): New
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HeaderInclude entry.
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@ -425,8 +428,7 @@
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* config/iq2000/iq2000-opts.h: New.
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* config/iq2000/iq2000.c: Don't include opts.h.
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(iq2000_tune, iq2000_handle_option, TARGET_HANDLE_OPTION): Remove.
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* config/iq2000/iq2000.h (enum processor_type, iq2000_tune):
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Remove.
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* config/iq2000/iq2000.h (enum processor_type, iq2000_tune): Remove.
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* config/iq2000/iq2000.opt (config/iq2000/iq2000-opts.h): New
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HeaderInclude entry.
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(iq2000_tune): New Variable entry.
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@ -458,8 +460,7 @@
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(frv_cpu_type): Remove.
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* config/frv/frv.c: Don't include opts.h.
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(frv_cpu_type, frv_handle_option, TARGET_HANDLE_OPTION): Remove.
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* config/frv/frv.opt (config/frv/frv-opts.h): New HeaderInclude
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entry.
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* config/frv/frv.opt (config/frv/frv-opts.h): New HeaderInclude entry.
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(frv_cpu_type): New Variable entry.
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(frv_cpu): New Enum and EnumValue entries.
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@ -480,8 +481,7 @@
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not bfin_lib_id_given.
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(bfin_handle_option): Don't set bfin_lib_id_given. Access
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bfin_cpu_type, bfin_si_revision and bfin_workarounds via opts
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pointer. Use error_at. Don't assert that global structures are in
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use.
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pointer. Use error_at. Don't assert that global structures are in use.
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* config/bfin/bfin.h: Include bfin-opts.h.
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(enum bfin_cpu_type, bfin_cpu_t): Move to bfin-opts.h.
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(bfin_cpu_type, bfin_si_revision, bfin_workarounds): Remove.
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@ -496,8 +496,7 @@
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or -msoft-float here.
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* config/arm/arm.h (CPP_SPEC): Handle -mfloat-abi=*, not
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-msoft-float and -mhard-float.
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(OPTION_DEFAULT_SPECS): Don't handle -mhard-float and
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-msoft-float.
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(OPTION_DEFAULT_SPECS): Don't handle -mhard-float and -msoft-float.
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* config/arm/coff.h (MULTILIB_DEFAULTS): Use mfloat-abi=soft, not
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msoft-float.
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* config/arm/elf.h (ASM_SPEC): Don't handle -mhard-float and
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@ -557,8 +556,7 @@
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global structures are in use.
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(ix86_function_specific_save, ix86_function_specific_restore):
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Update ix86_isa_flags_explicit field name.
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* config/i386/i386.opt (ix86_isa_flags_explicit): New Variable
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entry.
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* config/i386/i386.opt (ix86_isa_flags_explicit): New Variable entry.
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(ix86_isa_flags_explicit): Rename TargetSave entry to
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x_ix86_isa_flags_explicit.
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@ -813,8 +811,7 @@
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macro.
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(default_function_incoming_arg): Likewise.
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(default_function_arg_advance): Likewise.
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* target.def (function_arg, function_incoming_arg): Change to
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DEFHOOK.
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* target.def (function_arg, function_incoming_arg): Change to DEFHOOK.
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(function_arg_advance): Likewise.
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* target-def.h: Eliminate FUNCTION_INCOMING_ARG check.
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@ -890,7 +887,8 @@
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* function.c (safe_insn_predicate, assign_parm_setup_reg): Likewise.
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* optabs.c (can_compare_p, prepare_cmp_insn): Likewise.
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(emit_cmp_and_jump_insn_1, gen_add2_insn, gen_add3_insn): Likewise.
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(have_add2_insn, gen_sub2_insn, gen_sub3_insn, have_sub2_insn): Likewise.
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(have_add2_insn, gen_sub2_insn, gen_sub3_insn, have_sub2_insn):
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Likewise.
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(gen_cond_trap): Likewise.
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(prepare_operand): Likewise. Change icode to an insn_code.
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(insn_operand_matches): New function.
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@ -14398,17 +14398,26 @@ ix86_print_operand (FILE *file, rtx x, int code)
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fprintf (file, "0x%08x", (unsigned int) l);
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}
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/* These float cases don't actually occur as immediate operands. */
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else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode)
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{
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char dstr[30];
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REAL_VALUE_TYPE r;
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long l[2];
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real_to_decimal (dstr, CONST_DOUBLE_REAL_VALUE (x), sizeof (dstr), 0, 1);
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fputs (dstr, file);
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REAL_VALUE_FROM_CONST_DOUBLE (r, x);
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REAL_VALUE_TO_TARGET_DOUBLE (r, l);
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if (ASSEMBLER_DIALECT == ASM_ATT)
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putc ('$', file);
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/* We can use %d if the number is <32 bits and positive. */
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if (l[1] || l[0] < 0)
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fprintf (file, "0x%lx%08lx",
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(unsigned long) l[1], (unsigned long) l[0]);
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else
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fprintf (file, HOST_WIDE_INT_PRINT_DEC, l[0]);
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}
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else if (GET_CODE (x) == CONST_DOUBLE
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&& GET_MODE (x) == XFmode)
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/* These float cases don't actually occur as immediate operands. */
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else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == XFmode)
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{
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char dstr[30];
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@ -2915,9 +2915,9 @@
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(define_insn "*movdf_internal_rex64"
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[(set (match_operand:DF 0 "nonimmediate_operand"
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"=f,m,f,r ,m ,Y2*x,Y2*x,Y2*x,m ,Yi,r ")
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"=f,m,f,r ,m,!r,!m,Y2*x,Y2*x,Y2*x,m ,Yi,r ")
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(match_operand:DF 1 "general_operand"
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"fm,f,G,rmF,Fr,C ,Y2*x,m ,Y2*x,r ,Yi"))]
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"fm,f,G,rm,r,F ,F ,C ,Y2*x,m ,Y2*x,r ,Yi"))]
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"TARGET_64BIT && !(MEM_P (operands[0]) && MEM_P (operands[1]))
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&& (reload_in_progress || reload_completed
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|| (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
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@ -2938,9 +2938,15 @@
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case 3:
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case 4:
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return "#";
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return "mov{q}\t{%1, %0|%0, %1}";
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case 5:
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return "movabs{q}\t{%1, %0|%0, %1}";
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case 6:
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return "#";
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case 7:
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switch (get_attr_mode (insn))
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{
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case MODE_V4SF:
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@ -2958,9 +2964,9 @@
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default:
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gcc_unreachable ();
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}
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case 6:
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case 7:
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case 8:
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case 9:
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case 10:
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switch (get_attr_mode (insn))
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{
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case MODE_V4SF:
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@ -2995,17 +3001,27 @@
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gcc_unreachable ();
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}
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case 9:
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case 10:
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case 11:
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case 12:
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return "%vmovd\t{%1, %0|%0, %1}";
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default:
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gcc_unreachable();
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}
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}
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[(set_attr "type" "fmov,fmov,fmov,multi,multi,sselog1,ssemov,ssemov,ssemov,ssemov,ssemov")
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[(set_attr "type" "fmov,fmov,fmov,imov,imov,imov,multi,sselog1,ssemov,ssemov,ssemov,ssemov,ssemov")
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(set (attr "modrm")
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(if_then_else
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(and (eq_attr "alternative" "5") (eq_attr "type" "imov"))
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(const_string "0")
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(const_string "*")))
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(set (attr "length_immediate")
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(if_then_else
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(and (eq_attr "alternative" "5") (eq_attr "type" "imov"))
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(const_string "8")
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(const_string "*")))
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(set (attr "prefix")
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(if_then_else (eq_attr "alternative" "0,1,2,3,4")
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(if_then_else (eq_attr "alternative" "0,1,2,3,4,5,6")
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(const_string "orig")
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(const_string "maybe_vex")))
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(set (attr "prefix_data16")
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@ -3015,18 +3031,18 @@
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(set (attr "mode")
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(cond [(eq_attr "alternative" "0,1,2")
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(const_string "DF")
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(eq_attr "alternative" "3,4,9,10")
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(eq_attr "alternative" "3,4,5,6,11,12")
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(const_string "DI")
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/* For SSE1, we have many fewer alternatives. */
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(eq (symbol_ref "TARGET_SSE2") (const_int 0))
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(cond [(eq_attr "alternative" "5,6")
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(cond [(eq_attr "alternative" "7,8")
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(const_string "V4SF")
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]
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(const_string "V2SF"))
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/* xorps is one byte shorter. */
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(eq_attr "alternative" "5")
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(eq_attr "alternative" "7")
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(cond [(ne (symbol_ref "optimize_function_for_size_p (cfun)")
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(const_int 0))
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(const_string "V4SF")
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@ -3041,7 +3057,7 @@
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chains, otherwise use short move to avoid extra work.
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movaps encodes one byte shorter. */
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(eq_attr "alternative" "6")
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(eq_attr "alternative" "8")
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(cond
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[(ne (symbol_ref "optimize_function_for_size_p (cfun)")
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(const_int 0))
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@ -3054,7 +3070,7 @@
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/* For architectures resolving dependencies on register
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parts we may avoid extra work to zero out upper part
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of register. */
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(eq_attr "alternative" "7")
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(eq_attr "alternative" "9")
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(if_then_else
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(ne (symbol_ref "TARGET_SSE_SPLIT_REGS")
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(const_int 0))
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@ -3068,7 +3084,7 @@
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"=f,m,f,r ,o ,Y2*x,Y2*x,Y2*x,m ")
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(match_operand:DF 1 "general_operand"
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"fm,f,G,roF,Fr,C ,Y2*x,m ,Y2*x"))]
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"!(MEM_P (operands[0]) && MEM_P (operands[1]))
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"!TARGET_64BIT && !(MEM_P (operands[0]) && MEM_P (operands[1]))
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&& optimize_function_for_speed_p (cfun)
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&& TARGET_INTEGER_DFMODE_MOVES
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&& (reload_in_progress || reload_completed
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@ -3208,9 +3224,9 @@
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"=f,m,f,*r ,o ,Y2*x,Y2*x,Y2*x ,m ")
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(match_operand:DF 1 "general_operand"
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"fm,f,G,*roF,*Fr,C ,Y2*x,mY2*x,Y2*x"))]
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"!(MEM_P (operands[0]) && MEM_P (operands[1]))
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&& ((optimize_function_for_size_p (cfun)
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|| !TARGET_INTEGER_DFMODE_MOVES) && !TARGET_64BIT)
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"!TARGET_64BIT && !(MEM_P (operands[0]) && MEM_P (operands[1]))
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&& (optimize_function_for_size_p (cfun)
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|| !TARGET_INTEGER_DFMODE_MOVES)
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&& (reload_in_progress || reload_completed
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|| (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
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|| (!(TARGET_SSE2 && TARGET_SSE_MATH)
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@ -1,3 +1,8 @@
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2011-03-24 Uros Bizjak <ubizjak@gmail.com>
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PR target/48237
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* gcc.target/i386/pr48237.c: New test.
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2011-03-24 Richard Guenther <rguenther@suse.de>
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PR middle-end/48269
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@ -328,7 +333,7 @@
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2011-03-15 Rodrigo Rivas Costa <rodrigorivascosta@gmail.com>
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* g++.dg/cpp0x/constexpr-attribute.C: New.
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* g++.dg/cpp0x/constexpr-attribute.C: New.
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2011-03-15 Manuel López-Ibáñez <manu@gcc.gnu.org>
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22
gcc/testsuite/gcc.target/i386/pr48237.c
Normal file
22
gcc/testsuite/gcc.target/i386/pr48237.c
Normal file
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@ -0,0 +1,22 @@
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/* { dg-do compile } */
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/* { dg-options "-O -fcaller-saves -fschedule-insns2 -fselective-scheduling2 -mtune=core2" } */
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union double_union
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{
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double d;
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int i[2];
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};
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void bar (int, ...);
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void
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foo (double d)
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{
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union double_union du = { d };
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while (1)
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{
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du.i[1] -= 0x100000L;
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bar (0, du.d);
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du.d += d;
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}
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}
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Loading…
Add table
Reference in a new issue