[multiple changes]
Wed Nov 3 15:11:27 1999 David S. Miller <davem@redhat.com>
* config/sparc/sparc.md: Remove insn type fpsqrt, add fpsqrts
and fpsqrtd. Use them and create fdiv function unit to more
accurately represent fpu sqrt pipeline semantics on UltraSparc.
* config/sparc/sparc.c: Account for fpsqrt{s,d} changes.
Wed Nov 3 15:11:27 1999 Matteo Frigo <athena@fftw.org>
* config/sparc/sparc.md: Adjust FADD/FMUL result latencies to
3 on UltraSparc.
* config/sparc/sparc.c (ultra_schedule_insn): Insert launched
insn into ready list, do not use just a raw swap.
From-SVN: r30386
This commit is contained in:
David S. Miller
parent
aeeeda0391
commit
c0ec7a7575
3 changed files with 52 additions and 24 deletions
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@ -1,3 +1,17 @@
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Wed Nov 3 15:11:27 1999 David S. Miller <davem@redhat.com>
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* config/sparc/sparc.md: Remove insn type fpsqrt, add fpsqrts
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and fpsqrtd. Use them and create fdiv function unit to more
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accurately represent fpu sqrt pipeline semantics on UltraSparc.
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* config/sparc/sparc.c: Account for fpsqrt{s,d} changes.
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Wed Nov 3 15:11:27 1999 Matteo Frigo <athena@fftw.org>
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* config/sparc/sparc.md: Adjust FADD/FMUL result latencies to
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3 on UltraSparc.
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* config/sparc/sparc.c (ultra_schedule_insn): Insert launched
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insn into ready list, do not use just a raw swap.
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Wed Nov 3 14:51:59 1999 Mark P. Mitchell <mark@codesourcery.com>
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* rtl.h (renumber_insns): New function.
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@ -6475,7 +6475,8 @@ ultrasparc_adjust_cost (insn, link, dep_insn, cost)
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return 0;
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#define SLOW_FP(dep_type) \
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(dep_type == TYPE_FPSQRT || dep_type == TYPE_FPDIVS || dep_type == TYPE_FPDIVD)
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(dep_type == TYPE_FPSQRTS || dep_type == TYPE_FPSQRTD || \
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dep_type == TYPE_FPDIVS || dep_type == TYPE_FPDIVD)
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switch (REG_NOTE_KIND (link))
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{
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@ -6701,7 +6702,8 @@ ultra_code_from_mask (type_mask)
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TMASK (TYPE_FPSTORE)))
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return LSU;
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else if (type_mask & (TMASK (TYPE_FPMUL) | TMASK (TYPE_FPDIVS) |
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TMASK (TYPE_FPDIVD) | TMASK (TYPE_FPSQRT)))
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TMASK (TYPE_FPDIVD) | TMASK (TYPE_FPSQRTS) |
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TMASK (TYPE_FPSQRTD)))
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return FPM;
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else if (type_mask & (TMASK (TYPE_FPMOVE) | TMASK (TYPE_FPCMOVE) |
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TMASK (TYPE_FP) | TMASK (TYPE_FPCMP)))
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@ -6780,7 +6782,8 @@ ultra_fpmode_conflict_exists (fpmode)
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&& GET_CODE (SET_SRC (pat)) != NEG
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&& ((TMASK (get_attr_type (insn)) &
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(TMASK (TYPE_FPDIVS) | TMASK (TYPE_FPDIVD) |
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TMASK (TYPE_FPMOVE) | TMASK (TYPE_FPSQRT) |
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TMASK (TYPE_FPMOVE) | TMASK (TYPE_FPSQRTS) |
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TMASK (TYPE_FPSQRTD) |
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TMASK (TYPE_LOAD) | TMASK (TYPE_STORE))) == 0))
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return 1;
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}
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@ -6938,6 +6941,7 @@ ultra_schedule_insn (ip, ready, this, type)
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{
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int pipe_slot;
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char mask = ultra_pipe.free_slot_mask;
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rtx temp;
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/* Obtain free slot. */
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for (pipe_slot = 0; pipe_slot < 4; pipe_slot++)
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@ -6959,13 +6963,13 @@ ultra_schedule_insn (ip, ready, this, type)
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ultra_pipe.commit[pipe_slot] = 0;
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/* Update ready list. */
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if (ip != &ready[this])
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temp = *ip;
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while (ip != &ready[this])
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{
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rtx temp = *ip;
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*ip = ready[this];
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ready[this] = temp;
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ip[0] = ip[1];
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++ip;
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}
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*ip = temp;
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}
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/* Advance to the next pipeline group. */
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@ -7170,7 +7174,8 @@ ultrasparc_sched_reorder (dump, sched_verbose, ready, n_ready)
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}
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else if ((ip = ultra_find_type ((TMASK (TYPE_FPDIVS) |
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TMASK (TYPE_FPDIVD) |
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TMASK (TYPE_FPSQRT)),
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TMASK (TYPE_FPSQRTS) |
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TMASK (TYPE_FPSQRTD)),
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ready, this_insn)) != 0)
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{
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ultra_schedule_insn (ip, ready, this_insn, FPM);
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@ -98,7 +98,7 @@
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;; type "call_no_delay_slot" is a call followed by an unimp instruction.
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(define_attr "type"
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"move,unary,binary,compare,load,sload,store,ialu,shift,uncond_branch,branch,call,call_no_delay_slot,return,address,imul,fpload,fpstore,fp,fpmove,fpcmove,fpcmp,fpmul,fpdivs,fpdivd,fpsqrt,cmove,multi,misc"
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"move,unary,binary,compare,load,sload,store,ialu,shift,uncond_branch,branch,call,call_no_delay_slot,return,address,imul,fpload,fpstore,fp,fpmove,fpcmove,fpcmp,fpmul,fpdivs,fpdivd,fpsqrts,fpsqrtd,cmove,multi,misc"
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(const_string "binary"))
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;; Set true if insn uses call-clobbered intermediate register.
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@ -273,7 +273,7 @@
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(define_function_unit "fp_mds" 1 0
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(and (eq_attr "cpu" "cypress")
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(eq_attr "type" "fpsqrt"))
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(eq_attr "type" "fpsqrts,fpsqrtd"))
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63 63)
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;; ----- The TMS390Z55 scheduling
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@ -340,7 +340,7 @@
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(define_function_unit "fp_mds" 1 0
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(and (eq_attr "cpu" "supersparc")
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(eq_attr "type" "fpsqrt"))
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(eq_attr "type" "fpsqrts,fpsqrtd"))
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12 10)
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(define_function_unit "fp_mds" 1 0
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@ -387,7 +387,7 @@
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(define_function_unit "fp_mds" 1 0
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(and (ior (eq_attr "cpu" "hypersparc") (eq_attr "cpu" "sparclite86x"))
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(eq_attr "type" "fpsqrt"))
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(eq_attr "type" "fpsqrts,fpsqrtd"))
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17 15)
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(define_function_unit "fp_mds" 1 0
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@ -478,14 +478,18 @@
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;; Timings; throughput/latency
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;; FMOV 1/1 fmov, fabs, fneg
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;; FMOVcc 1/2
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;; FADD 1/4 add/sub, format conv, compar
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;; FMUL 1/4
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;; FADD 1/3 add/sub, format conv, compar
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;; FMUL 1/3
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;; FDIVs 12/12
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;; FDIVd 22/22
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;; FSQRTs 12/12
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;; FSQRTd 22/22
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;; FCMP takes 1 cycle to branch, 2 cycles to conditional move.
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;;
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;; FDIV{s,d}/FSQRT{s,d} are given their own unit since they only
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;; use the FPM multiplier for final rounding 3 cycles before the
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;; end of their latency and we have no real way to model that.
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;;
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;; ??? This is really bogus because the timings really depend upon
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;; who uses the result. We should record who the user is with
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;; more descriptive 'type' attribute names and account for these
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@ -504,7 +508,7 @@
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(define_function_unit "fadd" 1 0
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(and (eq_attr "cpu" "ultrasparc")
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(eq_attr "type" "fp"))
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4 1)
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3 1)
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(define_function_unit "fadd" 1 0
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(and (eq_attr "cpu" "ultrasparc")
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@ -514,27 +518,32 @@
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(define_function_unit "fmul" 1 0
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(and (eq_attr "cpu" "ultrasparc")
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(eq_attr "type" "fpmul"))
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4 1)
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3 1)
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(define_function_unit "fadd" 1 0
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(and (eq_attr "cpu" "ultrasparc")
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(eq_attr "type" "fpcmove"))
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2 1)
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(define_function_unit "fmul" 1 0
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(define_function_unit "fdiv" 1 0
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(and (eq_attr "cpu" "ultrasparc")
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(eq_attr "type" "fpdivs"))
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12 12)
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(define_function_unit "fmul" 1 0
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(define_function_unit "fdiv" 1 0
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(and (eq_attr "cpu" "ultrasparc")
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(eq_attr "type" "fpdivd"))
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22 22)
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(define_function_unit "fmul" 1 0
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(define_function_unit "fdiv" 1 0
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(and (eq_attr "cpu" "ultrasparc")
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(eq_attr "type" "fpsqrt"))
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(eq_attr "type" "fpsqrts"))
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12 12)
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(define_function_unit "fdiv" 1 0
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(and (eq_attr "cpu" "ultrasparc")
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(eq_attr "type" "fpsqrtd"))
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22 22)
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;; Compare instructions.
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;; This controls RTL generation and register allocation.
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@ -6884,7 +6893,7 @@
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(sqrt:TF (match_operand:TF 1 "register_operand" "e")))]
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"TARGET_FPU && TARGET_HARD_QUAD"
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"fsqrtq\\t%1, %0"
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[(set_attr "type" "fpsqrt")
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[(set_attr "type" "fpsqrtd")
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(set_attr "length" "1")])
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(define_insn "sqrtdf2"
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@ -6892,7 +6901,7 @@
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(sqrt:DF (match_operand:DF 1 "register_operand" "e")))]
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"TARGET_FPU"
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"fsqrtd\\t%1, %0"
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[(set_attr "type" "fpsqrt")
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[(set_attr "type" "fpsqrtd")
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(set_attr "length" "1")])
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(define_insn "sqrtsf2"
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@ -6900,7 +6909,7 @@
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(sqrt:SF (match_operand:SF 1 "register_operand" "f")))]
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"TARGET_FPU"
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"fsqrts\\t%1, %0"
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[(set_attr "type" "fpsqrt")
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[(set_attr "type" "fpsqrts")
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(set_attr "length" "1")])
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;;- arithmetic shift instructions
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