diff --git a/gcc/ChangeLog b/gcc/ChangeLog index efeee307aaa..573144367ae 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,17 @@ +Wed Nov 3 15:11:27 1999 David S. Miller + + * config/sparc/sparc.md: Remove insn type fpsqrt, add fpsqrts + and fpsqrtd. Use them and create fdiv function unit to more + accurately represent fpu sqrt pipeline semantics on UltraSparc. + * config/sparc/sparc.c: Account for fpsqrt{s,d} changes. + +Wed Nov 3 15:11:27 1999 Matteo Frigo + + * config/sparc/sparc.md: Adjust FADD/FMUL result latencies to + 3 on UltraSparc. + * config/sparc/sparc.c (ultra_schedule_insn): Insert launched + insn into ready list, do not use just a raw swap. + Wed Nov 3 14:51:59 1999 Mark P. Mitchell * rtl.h (renumber_insns): New function. diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c index 09256d2c49b..4592ceceddb 100644 --- a/gcc/config/sparc/sparc.c +++ b/gcc/config/sparc/sparc.c @@ -6475,7 +6475,8 @@ ultrasparc_adjust_cost (insn, link, dep_insn, cost) return 0; #define SLOW_FP(dep_type) \ -(dep_type == TYPE_FPSQRT || dep_type == TYPE_FPDIVS || dep_type == TYPE_FPDIVD) +(dep_type == TYPE_FPSQRTS || dep_type == TYPE_FPSQRTD || \ + dep_type == TYPE_FPDIVS || dep_type == TYPE_FPDIVD) switch (REG_NOTE_KIND (link)) { @@ -6701,7 +6702,8 @@ ultra_code_from_mask (type_mask) TMASK (TYPE_FPSTORE))) return LSU; else if (type_mask & (TMASK (TYPE_FPMUL) | TMASK (TYPE_FPDIVS) | - TMASK (TYPE_FPDIVD) | TMASK (TYPE_FPSQRT))) + TMASK (TYPE_FPDIVD) | TMASK (TYPE_FPSQRTS) | + TMASK (TYPE_FPSQRTD))) return FPM; else if (type_mask & (TMASK (TYPE_FPMOVE) | TMASK (TYPE_FPCMOVE) | TMASK (TYPE_FP) | TMASK (TYPE_FPCMP))) @@ -6780,7 +6782,8 @@ ultra_fpmode_conflict_exists (fpmode) && GET_CODE (SET_SRC (pat)) != NEG && ((TMASK (get_attr_type (insn)) & (TMASK (TYPE_FPDIVS) | TMASK (TYPE_FPDIVD) | - TMASK (TYPE_FPMOVE) | TMASK (TYPE_FPSQRT) | + TMASK (TYPE_FPMOVE) | TMASK (TYPE_FPSQRTS) | + TMASK (TYPE_FPSQRTD) | TMASK (TYPE_LOAD) | TMASK (TYPE_STORE))) == 0)) return 1; } @@ -6938,6 +6941,7 @@ ultra_schedule_insn (ip, ready, this, type) { int pipe_slot; char mask = ultra_pipe.free_slot_mask; + rtx temp; /* Obtain free slot. */ for (pipe_slot = 0; pipe_slot < 4; pipe_slot++) @@ -6959,13 +6963,13 @@ ultra_schedule_insn (ip, ready, this, type) ultra_pipe.commit[pipe_slot] = 0; /* Update ready list. */ - if (ip != &ready[this]) + temp = *ip; + while (ip != &ready[this]) { - rtx temp = *ip; - - *ip = ready[this]; - ready[this] = temp; + ip[0] = ip[1]; + ++ip; } + *ip = temp; } /* Advance to the next pipeline group. */ @@ -7170,7 +7174,8 @@ ultrasparc_sched_reorder (dump, sched_verbose, ready, n_ready) } else if ((ip = ultra_find_type ((TMASK (TYPE_FPDIVS) | TMASK (TYPE_FPDIVD) | - TMASK (TYPE_FPSQRT)), + TMASK (TYPE_FPSQRTS) | + TMASK (TYPE_FPSQRTD)), ready, this_insn)) != 0) { ultra_schedule_insn (ip, ready, this_insn, FPM); diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md index db1609b75e6..c15dbbe3076 100644 --- a/gcc/config/sparc/sparc.md +++ b/gcc/config/sparc/sparc.md @@ -98,7 +98,7 @@ ;; type "call_no_delay_slot" is a call followed by an unimp instruction. (define_attr "type" - "move,unary,binary,compare,load,sload,store,ialu,shift,uncond_branch,branch,call,call_no_delay_slot,return,address,imul,fpload,fpstore,fp,fpmove,fpcmove,fpcmp,fpmul,fpdivs,fpdivd,fpsqrt,cmove,multi,misc" + "move,unary,binary,compare,load,sload,store,ialu,shift,uncond_branch,branch,call,call_no_delay_slot,return,address,imul,fpload,fpstore,fp,fpmove,fpcmove,fpcmp,fpmul,fpdivs,fpdivd,fpsqrts,fpsqrtd,cmove,multi,misc" (const_string "binary")) ;; Set true if insn uses call-clobbered intermediate register. @@ -273,7 +273,7 @@ (define_function_unit "fp_mds" 1 0 (and (eq_attr "cpu" "cypress") - (eq_attr "type" "fpsqrt")) + (eq_attr "type" "fpsqrts,fpsqrtd")) 63 63) ;; ----- The TMS390Z55 scheduling @@ -340,7 +340,7 @@ (define_function_unit "fp_mds" 1 0 (and (eq_attr "cpu" "supersparc") - (eq_attr "type" "fpsqrt")) + (eq_attr "type" "fpsqrts,fpsqrtd")) 12 10) (define_function_unit "fp_mds" 1 0 @@ -387,7 +387,7 @@ (define_function_unit "fp_mds" 1 0 (and (ior (eq_attr "cpu" "hypersparc") (eq_attr "cpu" "sparclite86x")) - (eq_attr "type" "fpsqrt")) + (eq_attr "type" "fpsqrts,fpsqrtd")) 17 15) (define_function_unit "fp_mds" 1 0 @@ -478,14 +478,18 @@ ;; Timings; throughput/latency ;; FMOV 1/1 fmov, fabs, fneg ;; FMOVcc 1/2 -;; FADD 1/4 add/sub, format conv, compar -;; FMUL 1/4 +;; FADD 1/3 add/sub, format conv, compar +;; FMUL 1/3 ;; FDIVs 12/12 ;; FDIVd 22/22 ;; FSQRTs 12/12 ;; FSQRTd 22/22 ;; FCMP takes 1 cycle to branch, 2 cycles to conditional move. ;; +;; FDIV{s,d}/FSQRT{s,d} are given their own unit since they only +;; use the FPM multiplier for final rounding 3 cycles before the +;; end of their latency and we have no real way to model that. +;; ;; ??? This is really bogus because the timings really depend upon ;; who uses the result. We should record who the user is with ;; more descriptive 'type' attribute names and account for these @@ -504,7 +508,7 @@ (define_function_unit "fadd" 1 0 (and (eq_attr "cpu" "ultrasparc") (eq_attr "type" "fp")) - 4 1) + 3 1) (define_function_unit "fadd" 1 0 (and (eq_attr "cpu" "ultrasparc") @@ -514,27 +518,32 @@ (define_function_unit "fmul" 1 0 (and (eq_attr "cpu" "ultrasparc") (eq_attr "type" "fpmul")) - 4 1) + 3 1) (define_function_unit "fadd" 1 0 (and (eq_attr "cpu" "ultrasparc") (eq_attr "type" "fpcmove")) 2 1) -(define_function_unit "fmul" 1 0 +(define_function_unit "fdiv" 1 0 (and (eq_attr "cpu" "ultrasparc") (eq_attr "type" "fpdivs")) 12 12) -(define_function_unit "fmul" 1 0 +(define_function_unit "fdiv" 1 0 (and (eq_attr "cpu" "ultrasparc") (eq_attr "type" "fpdivd")) 22 22) -(define_function_unit "fmul" 1 0 +(define_function_unit "fdiv" 1 0 (and (eq_attr "cpu" "ultrasparc") - (eq_attr "type" "fpsqrt")) + (eq_attr "type" "fpsqrts")) 12 12) + +(define_function_unit "fdiv" 1 0 + (and (eq_attr "cpu" "ultrasparc") + (eq_attr "type" "fpsqrtd")) + 22 22) ;; Compare instructions. ;; This controls RTL generation and register allocation. @@ -6884,7 +6893,7 @@ (sqrt:TF (match_operand:TF 1 "register_operand" "e")))] "TARGET_FPU && TARGET_HARD_QUAD" "fsqrtq\\t%1, %0" - [(set_attr "type" "fpsqrt") + [(set_attr "type" "fpsqrtd") (set_attr "length" "1")]) (define_insn "sqrtdf2" @@ -6892,7 +6901,7 @@ (sqrt:DF (match_operand:DF 1 "register_operand" "e")))] "TARGET_FPU" "fsqrtd\\t%1, %0" - [(set_attr "type" "fpsqrt") + [(set_attr "type" "fpsqrtd") (set_attr "length" "1")]) (define_insn "sqrtsf2" @@ -6900,7 +6909,7 @@ (sqrt:SF (match_operand:SF 1 "register_operand" "f")))] "TARGET_FPU" "fsqrts\\t%1, %0" - [(set_attr "type" "fpsqrt") + [(set_attr "type" "fpsqrts") (set_attr "length" "1")]) ;;- arithmetic shift instructions