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RISC-V: Support simplifying x/(-1) to neg for vector.

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gcc/ChangeLog:

	* simplify-rtx.cc (simplify_context::simplify_binary_operation_1):
	support simplifying vector int not only scalar int.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/simplify-vdiv.c: New test.

Signed-off-by: Yanzhang Wang <yanzhang.wang@intel.com>
This commit is contained in:
Yanzhang Wang 2023-09-20 11:36:20 +08:00 • committed by Pan Li
parent b34397857a
commit b9cb735fc1
2 changed files with 20 additions and 2 deletions
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4
gcc/simplify-rtx.cc
View file

@ -4093,7 +4093,7 @@ simplify_context::simplify_binary_operation_1 (rtx_code code,
}
}
}
else if (SCALAR_INT_MODE_P (mode))
else if (SCALAR_INT_MODE_P (mode) || GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
{
/* 0/x is 0 (or x&0 if x has side-effects). */
if (trueop0 == CONST0_RTX (mode)
@ -4111,7 +4111,7 @@ simplify_context::simplify_binary_operation_1 (rtx_code code,
return tem;
}
/* x/-1 is -x. */
if (trueop1 == constm1_rtx)
if (trueop1 == CONSTM1_RTX (mode))
{
rtx x = rtl_hooks.gen_lowpart_no_emit (mode, op0);
if (x)

18
gcc/testsuite/gcc.target/riscv/rvv/base/simplify-vdiv.c Normal file
View file

@ -0,0 +1,18 @@
/* { dg-do compile } */
/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
#include "riscv_vector.h"
#define VDIV_WITH_LMUL(LMUL, DTYPE) \
vint##DTYPE##m##LMUL##_t \
shortcut_for_riscv_vdiv_case_##LMUL##_##DTYPE \
(vint##DTYPE##m##LMUL##_t v1, \
size_t vl) \
{ \
return __riscv_vdiv_vx_i##DTYPE##m##LMUL (v1, -1, vl); \
}
VDIV_WITH_LMUL (1, 16)
VDIV_WITH_LMUL (1, 32)
/* { dg-final { scan-assembler-times {vneg\.v} 2 } } */