RISC-V: Support VLS floating-point extend/truncate
Regression passed. Committed. gcc/ChangeLog: * config/riscv/vector-iterators.md: Extend VLS floating-point. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/widen/widen-10.c: Adapt test. * gcc.target/riscv/rvv/autovec/widen/widen-11.c: Ditto. * gcc.target/riscv/rvv/autovec/widen/widen-12.c: Ditto. * gcc.target/riscv/rvv/autovec/widen/widen-complicate-7.c: Ditto. * gcc.target/riscv/rvv/autovec/widen/widen-complicate-8.c: Ditto. * gcc.target/riscv/rvv/autovec/widen/widen-complicate-9.c: Ditto. * gcc.target/riscv/rvv/autovec/vls/ext-4.c: New test. * gcc.target/riscv/rvv/autovec/vls/ext-5.c: New test. * gcc.target/riscv/rvv/autovec/vls/trunc-4.c: New test. * gcc.target/riscv/rvv/autovec/vls/trunc-5.c: New test.
This commit is contained in:
Juzhe-Zhong
Lehua Ding
parent
c3d2b6bc91
commit
b34397857a
11 changed files with 225 additions and 6 deletions
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@ -994,6 +994,28 @@
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(RVVM8DF "TARGET_VECTOR_ELEN_FP_64") (RVVM4DF "TARGET_VECTOR_ELEN_FP_64")
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(RVVM2DF "TARGET_VECTOR_ELEN_FP_64") (RVVM1DF "TARGET_VECTOR_ELEN_FP_64")
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(V1SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
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(V2SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
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(V4SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
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(V8SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
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(V16SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 64")
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(V32SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
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(V64SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 256")
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(V128SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 512")
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(V256SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 1024")
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(V512SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 2048")
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(V1024SF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 4096")
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(V1DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64")
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(V2DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64")
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(V4DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64")
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(V8DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 64")
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(V16DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 128")
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(V32DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 256")
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(V64DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 512")
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(V128DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 1024")
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(V256DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 2048")
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(V512DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 4096")
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])
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(define_mode_iterator VWEXTF [
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@ -1049,6 +1071,17 @@
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(define_mode_iterator VQEXTF [
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(RVVM8DF "TARGET_VECTOR_ELEN_FP_64") (RVVM4DF "TARGET_VECTOR_ELEN_FP_64")
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(RVVM2DF "TARGET_VECTOR_ELEN_FP_64") (RVVM1DF "TARGET_VECTOR_ELEN_FP_64")
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(V1DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64")
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(V2DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64")
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(V4DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64")
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(V8DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 64")
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(V16DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 128")
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(V32DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 256")
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(V64DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 512")
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(V128DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 1024")
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(V256DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 2048")
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(V512DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 4096")
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])
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(define_mode_iterator VOEXTI [
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@ -2343,6 +2376,27 @@
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(V128DI "V128SI")
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(V256DI "V256SI")
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(V512DI "V512SI")
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(V1SF "V1HF")
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(V2SF "V2HF")
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(V4SF "V4HF")
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(V8SF "V8HF")
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(V16SF "V16HF")
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(V32SF "V32HF")
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(V64SF "V64HF")
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(V128SF "V128HF")
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(V256SF "V256HF")
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(V512SF "V512HF")
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(V1024SF "V1024HF")
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(V1DF "V1SF")
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(V2DF "V2SF")
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(V4DF "V4SF")
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(V8DF "V8SF")
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(V16DF "V16SF")
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(V32DF "V32SF")
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(V64DF "V64SF")
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(V128DF "V128SF")
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(V256DF "V256SF")
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(V512DF "V512SF")
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])
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(define_mode_attr V_QUAD_TRUNC [
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@ -2373,6 +2427,16 @@
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(V128DI "V128HI")
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(V256DI "V256HI")
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(V512DI "V512HI")
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(V1DF "V1HF")
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(V2DF "V2HF")
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(V4DF "V4HF")
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(V8DF "V8HF")
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(V16DF "V16HF")
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(V32DF "V32HF")
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(V64DF "V64HF")
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(V128DF "V128HF")
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(V256DF "V256HF")
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(V512DF "V512HF")
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])
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(define_mode_attr V_OCT_TRUNC [
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@ -2435,6 +2499,27 @@
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(V128DI "v128si")
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(V256DI "v256si")
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(V512DI "v512si")
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(V1SF "v1hf")
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(V2SF "v2hf")
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(V4SF "v4hf")
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(V8SF "v8hf")
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(V16SF "v16hf")
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(V32SF "v32hf")
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(V64SF "v64hf")
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(V128SF "v128hf")
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(V256SF "v256hf")
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(V512SF "v512hf")
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(V1024SF "v1024hf")
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(V1DF "v1sf")
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(V2DF "v2sf")
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(V4DF "v4sf")
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(V8DF "v8sf")
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(V16DF "v16sf")
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(V32DF "v32sf")
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(V64DF "v64sf")
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(V128DF "v128sf")
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(V256DF "v256sf")
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(V512DF "v512sf")
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])
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(define_mode_attr v_quad_trunc [
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@ -2465,6 +2550,16 @@
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(V128DI "v128hi")
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(V256DI "v256hi")
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(V512DI "v512hi")
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(V1DF "v1hf")
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(V2DF "v2hf")
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(V4DF "v4hf")
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(V8DF "v8hf")
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(V16DF "v16hf")
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(V32DF "v32hf")
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(V64DF "v64hf")
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(V128DF "v128hf")
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(V256DF "v256hf")
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(V512DF "v512hf")
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])
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(define_mode_attr v_oct_trunc [
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35
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/ext-4.c
Normal file
35
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/ext-4.c
Normal file
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@ -0,0 +1,35 @@
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/* { dg-do compile } */
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/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
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#include "def.h"
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DEF_CONVERT (fwcvt, _Float16, float, 4)
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DEF_CONVERT (fwcvt, _Float16, float, 16)
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DEF_CONVERT (fwcvt, _Float16, float, 32)
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DEF_CONVERT (fwcvt, _Float16, float, 64)
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DEF_CONVERT (fwcvt, _Float16, float, 128)
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DEF_CONVERT (fwcvt, _Float16, float, 256)
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DEF_CONVERT (fwcvt, _Float16, float, 512)
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DEF_CONVERT (fwcvt, _Float16, float, 1024)
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DEF_CONVERT (fwcvt, float, double, 4)
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DEF_CONVERT (fwcvt, float, double, 16)
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DEF_CONVERT (fwcvt, float, double, 32)
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DEF_CONVERT (fwcvt, float, double, 64)
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DEF_CONVERT (fwcvt, float, double, 128)
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DEF_CONVERT (fwcvt, float, double, 256)
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/* { dg-final { scan-assembler-times {vfwcvt\.f\.f\.v} 14 } } */
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/* { dg-final { scan-assembler-not {csrr} } } */
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/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
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/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
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/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
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/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */
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/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */
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/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */
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/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */
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/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */
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/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */
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/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */
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/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */
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/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */
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27
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/ext-5.c
Normal file
27
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/ext-5.c
Normal file
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@ -0,0 +1,27 @@
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/* { dg-do compile } */
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/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
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#include "def.h"
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DEF_CONVERT (fwcvt, _Float16, double, 4)
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DEF_CONVERT (fwcvt, _Float16, double, 16)
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DEF_CONVERT (fwcvt, _Float16, double, 32)
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DEF_CONVERT (fwcvt, _Float16, double, 64)
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DEF_CONVERT (fwcvt, _Float16, double, 128)
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DEF_CONVERT (fwcvt, _Float16, double, 256)
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DEF_CONVERT (fwcvt, _Float16, double, 512)
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/* { dg-final { scan-assembler-times {vfwcvt\.f\.f\.v} 14 } } */
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/* { dg-final { scan-assembler-not {csrr} } } */
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/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
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/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
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/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
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/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */
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/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */
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/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */
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/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */
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/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */
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/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */
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/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */
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/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */
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/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */
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35
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trunc-4.c
Normal file
35
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trunc-4.c
Normal file
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@ -0,0 +1,35 @@
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/* { dg-do compile } */
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/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
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#include "def.h"
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DEF_CONVERT (fncvt, float, _Float16, 4)
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DEF_CONVERT (fncvt, float, _Float16, 16)
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DEF_CONVERT (fncvt, float, _Float16, 32)
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DEF_CONVERT (fncvt, float, _Float16, 64)
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DEF_CONVERT (fncvt, float, _Float16, 128)
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DEF_CONVERT (fncvt, float, _Float16, 256)
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DEF_CONVERT (fncvt, float, _Float16, 512)
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DEF_CONVERT (fncvt, float, _Float16, 1024)
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DEF_CONVERT (fncvt, double, float, 4)
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DEF_CONVERT (fncvt, double, float, 16)
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DEF_CONVERT (fncvt, double, float, 32)
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DEF_CONVERT (fncvt, double, float, 64)
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DEF_CONVERT (fncvt, double, float, 128)
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DEF_CONVERT (fncvt, double, float, 256)
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/* { dg-final { scan-assembler-times {vfncvt\.f\.f\.w} 14 } } */
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/* { dg-final { scan-assembler-not {csrr} } } */
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/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
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/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
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/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
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/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */
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/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */
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/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */
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/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */
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/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */
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/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */
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/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */
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/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */
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/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */
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27
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trunc-5.c
Normal file
27
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/trunc-5.c
Normal file
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@ -0,0 +1,27 @@
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/* { dg-do compile } */
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/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
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#include "def.h"
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DEF_CONVERT (fncvt, double, _Float16, 4)
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DEF_CONVERT (fncvt, double, _Float16, 16)
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DEF_CONVERT (fncvt, double, _Float16, 32)
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DEF_CONVERT (fncvt, double, _Float16, 64)
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DEF_CONVERT (fncvt, double, _Float16, 128)
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DEF_CONVERT (fncvt, double, _Float16, 256)
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DEF_CONVERT (fncvt, double, _Float16, 512)
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/* { dg-final { scan-assembler-times {vfncvt} 14 } } */
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/* { dg-final { scan-assembler-not {csrr} } } */
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/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
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/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
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/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
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/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */
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/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */
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/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */
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/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */
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/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */
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/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */
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/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */
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/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */
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/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */
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/* { dg-do compile } */
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/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -O3 -ffast-math" } */
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/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -O3 -ffast-math -fno-vect-cost-model" } */
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#include <stdint-gcc.h>
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@ -1,5 +1,5 @@
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/* { dg-do compile } */
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/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -O3 -ffast-math" } */
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/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -O3 -ffast-math -fno-vect-cost-model" } */
|
||||
|
||||
#include <stdint-gcc.h>
|
||||
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -O3 -ffast-math" } */
|
||||
/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -O3 -ffast-math -fno-vect-cost-model" } */
|
||||
|
||||
#include <stdint-gcc.h>
|
||||
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math" } */
|
||||
/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */
|
||||
|
||||
#include <stdint-gcc.h>
|
||||
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math" } */
|
||||
/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */
|
||||
|
||||
#include <stdint-gcc.h>
|
||||
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math" } */
|
||||
/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math -fno-vect-cost-model" } */
|
||||
|
||||
#include <stdint-gcc.h>
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue