RISC-V: Add RVV machine modes.
gcc/ChangeLog: * config/riscv/riscv-modes.def (VECTOR_BOOL_MODE): Add RVV mask modes. (ADJUST_NUNITS): Adjust nunits using riscv_vector_chunks. (ADJUST_ALIGNMENT): Adjust alignment. (ADJUST_BYTESIZE): Adjust bytesize using riscv_vector_chunks. (RVV_MODES): New macro. (VECTOR_MODE_WITH_PREFIX): Add RVV vector modes. (VECTOR_MODES_WITH_PREFIX): Add RVV vector modes.
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zhongjuzhe
Kito Cheng
parent
b4feb49cf3
commit
b2fe02b476
1 changed files with 141 additions and 0 deletions
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@ -22,6 +22,147 @@ along with GCC; see the file COPYING3. If not see
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FLOAT_MODE (HF, 2, ieee_half_format);
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FLOAT_MODE (TF, 16, ieee_quad_format);
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/* Vector modes. */
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/* Encode the ratio of SEW/LMUL into the mask types. There are the following
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* mask types. */
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/* | Mode | MIN_VLEN = 32 | MIN_VLEN = 64 |
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| | SEW/LMUL | SEW/LMUL |
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| VNx1BI | 32 | 64 |
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| VNx2BI | 16 | 32 |
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| VNx4BI | 8 | 16 |
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| VNx8BI | 4 | 8 |
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| VNx16BI | 2 | 4 |
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| VNx32BI | 1 | 2 |
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| VNx64BI | N/A | 1 | */
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VECTOR_BOOL_MODE (VNx1BI, 1, BI, 8);
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VECTOR_BOOL_MODE (VNx2BI, 2, BI, 8);
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VECTOR_BOOL_MODE (VNx4BI, 4, BI, 8);
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VECTOR_BOOL_MODE (VNx8BI, 8, BI, 8);
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VECTOR_BOOL_MODE (VNx16BI, 16, BI, 8);
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VECTOR_BOOL_MODE (VNx32BI, 32, BI, 8);
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VECTOR_BOOL_MODE (VNx64BI, 64, BI, 8);
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ADJUST_NUNITS (VNx1BI, riscv_vector_chunks * 1);
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ADJUST_NUNITS (VNx2BI, riscv_vector_chunks * 2);
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ADJUST_NUNITS (VNx4BI, riscv_vector_chunks * 4);
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ADJUST_NUNITS (VNx8BI, riscv_vector_chunks * 8);
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ADJUST_NUNITS (VNx16BI, riscv_vector_chunks * 16);
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ADJUST_NUNITS (VNx32BI, riscv_vector_chunks * 32);
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ADJUST_NUNITS (VNx64BI, riscv_vector_chunks * 64);
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ADJUST_ALIGNMENT (VNx1BI, 1);
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ADJUST_ALIGNMENT (VNx2BI, 1);
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ADJUST_ALIGNMENT (VNx4BI, 1);
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ADJUST_ALIGNMENT (VNx8BI, 1);
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ADJUST_ALIGNMENT (VNx16BI, 1);
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ADJUST_ALIGNMENT (VNx32BI, 1);
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ADJUST_ALIGNMENT (VNx64BI, 1);
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ADJUST_BYTESIZE (VNx1BI, riscv_vector_chunks * riscv_bytes_per_vector_chunk);
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ADJUST_BYTESIZE (VNx2BI, riscv_vector_chunks * riscv_bytes_per_vector_chunk);
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ADJUST_BYTESIZE (VNx4BI, riscv_vector_chunks * riscv_bytes_per_vector_chunk);
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ADJUST_BYTESIZE (VNx8BI, riscv_vector_chunks * riscv_bytes_per_vector_chunk);
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ADJUST_BYTESIZE (VNx16BI, riscv_vector_chunks * riscv_bytes_per_vector_chunk);
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ADJUST_BYTESIZE (VNx32BI, riscv_vector_chunks * riscv_bytes_per_vector_chunk);
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ADJUST_BYTESIZE (VNx64BI, riscv_vector_chunks * riscv_bytes_per_vector_chunk);
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/*
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| Mode | MIN_VLEN=32 | MIN_VLEN=32 | MIN_VLEN=64 | MIN_VLEN=64 |
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| | LMUL | SEW/LMUL | LMUL | SEW/LMUL |
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| VNx1QI | MF4 | 32 | MF8 | 64 |
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| VNx2QI | MF2 | 16 | MF4 | 32 |
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| VNx4QI | M1 | 8 | MF2 | 16 |
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| VNx8QI | M2 | 4 | M1 | 8 |
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| VNx16QI | M4 | 2 | M2 | 4 |
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| VNx32QI | M8 | 1 | M4 | 2 |
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| VNx64QI | N/A | N/A | M8 | 1 |
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| VNx1(HI|HF) | MF2 | 32 | MF4 | 64 |
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| VNx2(HI|HF) | M1 | 16 | MF2 | 32 |
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| VNx4(HI|HF) | M2 | 8 | M1 | 16 |
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| VNx8(HI|HF) | M4 | 4 | M2 | 8 |
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| VNx16(HI|HF)| M8 | 2 | M4 | 4 |
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| VNx32(HI|HF)| N/A | N/A | M8 | 2 |
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| VNx1(SI|SF) | M1 | 32 | MF2 | 64 |
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| VNx2(SI|SF) | M2 | 16 | M1 | 32 |
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| VNx4(SI|SF) | M4 | 8 | M2 | 16 |
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| VNx8(SI|SF) | M8 | 4 | M4 | 8 |
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| VNx16(SI|SF)| N/A | N/A | M8 | 4 |
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| VNx1(DI|DF) | N/A | N/A | M1 | 64 |
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| VNx2(DI|DF) | N/A | N/A | M2 | 32 |
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| VNx4(DI|DF) | N/A | N/A | M4 | 16 |
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| VNx8(DI|DF) | N/A | N/A | M8 | 8 |
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*/
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/* Define RVV modes whose sizes are multiples of 64-bit chunks. */
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#define RVV_MODES(NVECS, VB, VH, VS, VD) \
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VECTOR_MODES_WITH_PREFIX (VNx, INT, 8 * NVECS, 0); \
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VECTOR_MODES_WITH_PREFIX (VNx, FLOAT, 8 * NVECS, 0); \
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\
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ADJUST_NUNITS (VB##QI, riscv_vector_chunks * NVECS * 8); \
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ADJUST_NUNITS (VH##HI, riscv_vector_chunks * NVECS * 4); \
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ADJUST_NUNITS (VS##SI, riscv_vector_chunks * NVECS * 2); \
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ADJUST_NUNITS (VD##DI, riscv_vector_chunks * NVECS); \
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ADJUST_NUNITS (VH##HF, riscv_vector_chunks * NVECS * 4); \
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ADJUST_NUNITS (VS##SF, riscv_vector_chunks * NVECS * 2); \
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ADJUST_NUNITS (VD##DF, riscv_vector_chunks * NVECS); \
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\
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ADJUST_ALIGNMENT (VB##QI, 1); \
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ADJUST_ALIGNMENT (VH##HI, 2); \
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ADJUST_ALIGNMENT (VS##SI, 4); \
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ADJUST_ALIGNMENT (VD##DI, 8); \
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ADJUST_ALIGNMENT (VH##HF, 2); \
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ADJUST_ALIGNMENT (VS##SF, 4); \
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ADJUST_ALIGNMENT (VD##DF, 8);
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/* 'VECTOR_MODES_WITH_PREFIX' does not allow ncomponents < 2.
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So we use 'VECTOR_MODE_WITH_PREFIX' to define VNx1DImode and VNx1DFmode. */
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VECTOR_MODE_WITH_PREFIX (VNx, INT, DI, 1, 0);
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VECTOR_MODE_WITH_PREFIX (VNx, FLOAT, DF, 1, 0);
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RVV_MODES (1, VNx8, VNx4, VNx2, VNx1)
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RVV_MODES (2, VNx16, VNx8, VNx4, VNx2)
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RVV_MODES (4, VNx32, VNx16, VNx8, VNx4)
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RVV_MODES (8, VNx64, VNx32, VNx16, VNx8)
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VECTOR_MODES_WITH_PREFIX (VNx, INT, 4, 0);
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VECTOR_MODES_WITH_PREFIX (VNx, FLOAT, 4, 0);
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ADJUST_NUNITS (VNx4QI, riscv_vector_chunks * 4);
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ADJUST_NUNITS (VNx2HI, riscv_vector_chunks * 2);
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ADJUST_NUNITS (VNx2HF, riscv_vector_chunks * 2);
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ADJUST_ALIGNMENT (VNx4QI, 1);
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ADJUST_ALIGNMENT (VNx2HI, 2);
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ADJUST_ALIGNMENT (VNx2HF, 2);
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/* 'VECTOR_MODES_WITH_PREFIX' does not allow ncomponents < 2.
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So we use 'VECTOR_MODE_WITH_PREFIX' to define VNx1SImode and VNx1SFmode. */
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VECTOR_MODE_WITH_PREFIX (VNx, INT, SI, 1, 0);
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VECTOR_MODE_WITH_PREFIX (VNx, FLOAT, SF, 1, 0);
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ADJUST_NUNITS (VNx1SI, riscv_vector_chunks);
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ADJUST_NUNITS (VNx1SF, riscv_vector_chunks);
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ADJUST_ALIGNMENT (VNx1SI, 4);
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ADJUST_ALIGNMENT (VNx1SF, 4);
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VECTOR_MODES_WITH_PREFIX (VNx, INT, 2, 0);
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ADJUST_NUNITS (VNx2QI, riscv_vector_chunks * 2);
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ADJUST_ALIGNMENT (VNx2QI, 1);
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/* 'VECTOR_MODES_WITH_PREFIX' does not allow ncomponents < 2.
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So we use 'VECTOR_MODE_WITH_PREFIX' to define VNx1HImode and VNx1HFmode. */
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VECTOR_MODE_WITH_PREFIX (VNx, INT, HI, 1, 0);
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VECTOR_MODE_WITH_PREFIX (VNx, FLOAT, HF, 1, 0);
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ADJUST_NUNITS (VNx1HI, riscv_vector_chunks);
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ADJUST_NUNITS (VNx1HF, riscv_vector_chunks);
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ADJUST_ALIGNMENT (VNx1HI, 2);
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ADJUST_ALIGNMENT (VNx1HF, 2);
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/* 'VECTOR_MODES_WITH_PREFIX' does not allow ncomponents < 2.
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So we use 'VECTOR_MODE_WITH_PREFIX' to define VNx1QImode. */
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VECTOR_MODE_WITH_PREFIX (VNx, INT, QI, 1, 0);
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ADJUST_NUNITS (VNx1QI, riscv_vector_chunks);
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ADJUST_ALIGNMENT (VNx1QI, 1);
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/* TODO: According to RISC-V 'V' ISA spec, the maximun vector length can
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be 65536 for a single vector register which means the vector mode in
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GCC can be maximum = 65536 * 8 bits (LMUL=8).
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