RISC-V: Support poly move manipulation and selftests.
gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Change "static void" to "void". * config.gcc: Add riscv-selftests.o * config/riscv/predicates.md: Allow const_poly_int. * config/riscv/riscv-protos.h (riscv_reinit): New function. (riscv_parse_arch_string): change as exten function. (riscv_run_selftests): New function. * config/riscv/riscv.cc (riscv_cannot_force_const_mem): Don't allow poly into const pool. (riscv_report_v_required): New function. (riscv_expand_op): New function. (riscv_expand_mult_with_const_int): New function. (riscv_legitimize_poly_move): Ditto. (riscv_legitimize_move): New function. (riscv_hard_regno_mode_ok): Add VL/VTYPE register allocation and fix vector RA. (riscv_convert_vector_bits): Fix riscv_vector_chunks configuration for -marh no 'v'. (riscv_reinit): New function. (TARGET_RUN_TARGET_SELFTESTS): New target hook support. * config/riscv/t-riscv: Add riscv-selftests.o. * config/riscv/riscv-selftests.cc: New file. gcc/testsuite/ChangeLog: * selftests/riscv/empty-func.rtl: New test.
This commit is contained in:
zhongjuzhe
Kito Cheng
parent
ab98b4c072
commit
b4feb49cf3
8 changed files with 560 additions and 7 deletions
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@ -1224,7 +1224,7 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
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/* Parse a RISC-V ISA string into an option mask. Must clear or set all arch
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dependent mask bits, in case more than one -march string is passed. */
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static void
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void
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riscv_parse_arch_string (const char *isa,
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struct gcc_options *opts,
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location_t loc)
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@ -515,7 +515,7 @@ pru-*-*)
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;;
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riscv*)
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cpu_type=riscv
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extra_objs="riscv-builtins.o riscv-c.o riscv-sr.o riscv-shorten-memrefs.o"
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extra_objs="riscv-builtins.o riscv-c.o riscv-sr.o riscv-shorten-memrefs.o riscv-selftests.o"
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d_target_objs="riscv-d.o"
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;;
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rs6000*-*-*)
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@ -146,6 +146,9 @@
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case CONST_INT:
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return !splittable_const_int_operand (op, mode);
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case CONST_POLY_INT:
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return known_eq (rtx_to_poly_int64 (op), BYTES_PER_RISCV_VECTOR);
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case CONST:
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case SYMBOL_REF:
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case LABEL_REF:
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@ -74,6 +74,7 @@ extern bool riscv_expand_block_move (rtx, rtx, rtx);
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extern bool riscv_store_data_bypass_p (rtx_insn *, rtx_insn *);
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extern rtx riscv_gen_gpr_save_insn (struct riscv_frame_info *);
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extern bool riscv_gpr_save_operation_p (rtx);
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extern void riscv_reinit (void);
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/* Routines implemented in riscv-c.cc. */
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void riscv_cpu_cpp_builtins (cpp_reader *);
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@ -86,6 +87,7 @@ extern void riscv_init_builtins (void);
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/* Routines implemented in riscv-common.cc. */
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extern std::string riscv_arch_str (bool version_p = true);
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extern void riscv_parse_arch_string (const char *, struct gcc_options *, location_t);
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extern bool riscv_hard_regno_rename_ok (unsigned, unsigned);
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@ -105,4 +107,11 @@ struct riscv_cpu_info {
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extern const riscv_cpu_info *riscv_find_cpu (const char *);
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/* Routines implemented in riscv-selftests.cc. */
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#if CHECKING_P
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namespace selftest {
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extern void riscv_run_selftests (void);
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} // namespace selftest
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#endif
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#endif /* ! GCC_RISCV_PROTOS_H */
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241
gcc/config/riscv/riscv-selftests.cc
Normal file
241
gcc/config/riscv/riscv-selftests.cc
Normal file
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@ -0,0 +1,241 @@
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/* This file is part of GCC.
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GCC is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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GCC is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with GCC; see the file COPYING3. If not see
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<http://www.gnu.org/licenses/>. */
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#define IN_TARGET_CODE 1
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#define INCLUDE_STRING
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#define INCLUDE_MAP
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#define INCLUDE_VECTOR
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#include "config.h"
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#include "system.h"
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#include "coretypes.h"
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#include "tm.h"
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#include "rtl.h"
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#include "tree.h"
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#include "stringpool.h"
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#include "function.h"
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#include "memmodel.h"
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#include "emit-rtl.h"
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#include "tm_p.h"
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#include "expr.h"
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#include "selftest.h"
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#include "selftest-rtl.h"
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#if CHECKING_P
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using namespace selftest;
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class riscv_selftest_arch_abi_setter
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{
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private:
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std::string m_arch_backup;
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enum riscv_abi_type m_abi_backup;
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public:
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riscv_selftest_arch_abi_setter (const char *arch, enum riscv_abi_type abi)
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: m_arch_backup (riscv_arch_str ()), m_abi_backup (riscv_abi)
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{
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riscv_parse_arch_string (arch, &global_options, UNKNOWN_LOCATION);
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riscv_abi = abi;
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riscv_reinit ();
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}
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~riscv_selftest_arch_abi_setter ()
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{
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riscv_parse_arch_string (m_arch_backup.c_str (), &global_options,
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UNKNOWN_LOCATION);
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riscv_abi = m_abi_backup;
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riscv_reinit ();
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}
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};
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static poly_int64
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eval_value (rtx x, std::map<unsigned, rtx> ®no_to_rtx)
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{
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if (!REG_P (x))
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{
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debug (x);
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gcc_unreachable ();
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}
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rtx expr = NULL_RTX;
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unsigned regno = REGNO (x);
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expr = regno_to_rtx[regno];
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poly_int64 op1_val = 0;
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poly_int64 op2_val = 0;
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if (UNARY_P (expr))
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{
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op1_val = eval_value (XEXP (expr, 0), regno_to_rtx);
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}
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if (BINARY_P (expr))
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{
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op1_val = eval_value (XEXP (expr, 0), regno_to_rtx);
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op2_val = eval_value (XEXP (expr, 1), regno_to_rtx);
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}
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switch (GET_CODE (expr))
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{
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case CONST_POLY_INT:
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return rtx_to_poly_int64 (expr);
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case CONST_INT:
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return INTVAL (expr);
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case MULT:
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if (op1_val.is_constant ())
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return op1_val.to_constant () * op2_val;
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else if (op2_val.is_constant ())
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return op1_val * op2_val.to_constant ();
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else
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gcc_unreachable ();
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case PLUS:
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return op1_val + op2_val;
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default:
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gcc_unreachable ();
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}
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}
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/* Calculate the value of x register in the sequence. */
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static poly_int64
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calculate_x_in_sequence (rtx reg)
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{
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std::map<unsigned, rtx> regno_to_rtx;
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rtx_insn *insn;
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for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
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{
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rtx pat = PATTERN (insn);
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rtx dest = SET_DEST (pat);
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if (GET_CODE (pat) == CLOBBER)
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continue;
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if (SUBREG_P (dest))
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continue;
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gcc_assert (REG_P (dest));
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rtx note = find_reg_equal_equiv_note (insn);
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unsigned regno = REGNO (dest);
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if (note)
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regno_to_rtx[regno] = XEXP (note, 0);
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else
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regno_to_rtx[regno] = SET_SRC (pat);
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}
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return eval_value (reg, regno_to_rtx);
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}
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typedef enum
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{
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POLY_TEST_DIMODE,
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POLY_TEST_PMODE
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} poly_test_mode_t;
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static void
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simple_poly_selftest (const char *arch, enum riscv_abi_type abi,
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const std::vector<machine_mode> &modes)
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{
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riscv_selftest_arch_abi_setter rv (arch, abi);
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rtl_dump_test t (SELFTEST_LOCATION, locate_file ("riscv/empty-func.rtl"));
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set_new_first_and_last_insn (NULL, NULL);
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for (machine_mode mode : modes)
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emit_move_insn (gen_reg_rtx (mode),
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gen_int_mode (BYTES_PER_RISCV_VECTOR, mode));
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}
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static void
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run_poly_int_selftest (const char *arch, enum riscv_abi_type abi,
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poly_test_mode_t test_mode,
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const std::vector<poly_int64> &worklist)
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{
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riscv_selftest_arch_abi_setter rv (arch, abi);
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rtl_dump_test t (SELFTEST_LOCATION, locate_file ("riscv/empty-func.rtl"));
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set_new_first_and_last_insn (NULL, NULL);
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machine_mode mode = VOIDmode;
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switch (test_mode)
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{
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case POLY_TEST_DIMODE:
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mode = DImode;
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break;
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case POLY_TEST_PMODE:
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mode = Pmode;
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break;
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default:
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gcc_unreachable ();
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}
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for (const poly_int64 &poly_val : worklist)
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{
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start_sequence ();
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rtx dest = gen_reg_rtx (mode);
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emit_move_insn (dest, gen_int_mode (poly_val, mode));
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ASSERT_TRUE (known_eq (calculate_x_in_sequence (dest), poly_val));
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end_sequence ();
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}
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}
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static void
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run_poly_int_selftests (void)
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{
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std::vector<poly_int64> worklist
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= {BYTES_PER_RISCV_VECTOR, BYTES_PER_RISCV_VECTOR * 8,
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BYTES_PER_RISCV_VECTOR * 32, -BYTES_PER_RISCV_VECTOR * 8,
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-BYTES_PER_RISCV_VECTOR * 32, BYTES_PER_RISCV_VECTOR * 7,
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BYTES_PER_RISCV_VECTOR * 31, -BYTES_PER_RISCV_VECTOR * 7,
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-BYTES_PER_RISCV_VECTOR * 31, BYTES_PER_RISCV_VECTOR * 9,
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BYTES_PER_RISCV_VECTOR * 33, -BYTES_PER_RISCV_VECTOR * 9,
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-BYTES_PER_RISCV_VECTOR * 33, poly_int64 (207, 0),
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poly_int64 (-207, 0), poly_int64 (0, 207),
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poly_int64 (0, -207), poly_int64 (5555, 0),
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poly_int64 (0, 5555), poly_int64 (4096, 4096),
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poly_int64 (17, 4088), poly_int64 (3889, 4104),
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poly_int64 (-4096, -4096), poly_int64 (219, -4088),
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poly_int64 (-4309, -4104), poly_int64 (-7337, 88),
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poly_int64 (9317, -88), poly_int64 (4, 4),
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poly_int64 (17, 4), poly_int64 (-7337, 4),
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poly_int64 (-4, -4), poly_int64 (-389, -4),
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poly_int64 (4789, -4), poly_int64 (-5977, 1508),
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poly_int64 (219, -1508), poly_int64 (2, 2),
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poly_int64 (33, 2), poly_int64 (-7337, 2),
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poly_int64 (-2, -2), poly_int64 (-389, -2),
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poly_int64 (4789, -2), poly_int64 (-3567, 954),
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poly_int64 (945, -954), poly_int64 (1, 1),
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poly_int64 (977, 1), poly_int64 (-339, 1),
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poly_int64 (-1, -1), poly_int64 (-12, -1),
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poly_int64 (44, -1), poly_int64 (9567, 77),
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poly_int64 (3467, -77)};
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simple_poly_selftest ("rv64imafdv", ABI_LP64D,
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{QImode, HImode, SImode, DImode});
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simple_poly_selftest ("rv32imafdv", ABI_ILP32D, {QImode, HImode, SImode});
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run_poly_int_selftest ("rv64imafdv", ABI_LP64D, POLY_TEST_PMODE, worklist);
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run_poly_int_selftest ("rv64imafd_zve32x1p0", ABI_LP64D, POLY_TEST_PMODE,
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worklist);
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run_poly_int_selftest ("rv32imafdv", ABI_ILP32, POLY_TEST_PMODE, worklist);
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run_poly_int_selftest ("rv32imafdv", ABI_ILP32, POLY_TEST_DIMODE, worklist);
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run_poly_int_selftest ("rv32imafd_zve32x1p0", ABI_ILP32D, POLY_TEST_PMODE,
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worklist);
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run_poly_int_selftest ("rv32imafd_zve32x1p0", ABI_ILP32D, POLY_TEST_DIMODE,
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worklist);
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}
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namespace selftest {
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/* Run all target-specific selftests. */
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void
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riscv_run_selftests (void)
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{
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run_poly_int_selftests ();
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}
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} // namespace selftest
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#endif /* #if CHECKING_P */
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@ -57,6 +57,8 @@ along with GCC; see the file COPYING3. If not see
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#include "predict.h"
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#include "tree-pass.h"
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#include "opts.h"
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#include "tm-constrs.h"
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#include "rtl-iter.h"
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/* True if X is an UNSPEC wrapper around a SYMBOL_REF or LABEL_REF. */
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#define UNSPEC_ADDRESS_P(X) \
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@ -778,6 +780,12 @@ riscv_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED, rtx x)
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enum riscv_symbol_type type;
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rtx base, offset;
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/* There's no way to calculate VL-based values using relocations. */
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subrtx_iterator::array_type array;
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FOR_EACH_SUBRTX (iter, array, x, ALL)
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if (GET_CODE (*iter) == CONST_POLY_INT)
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return true;
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/* There is no assembler syntax for expressing an address-sized
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high part. */
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if (GET_CODE (x) == HIGH)
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@ -1684,12 +1692,268 @@ riscv_legitimize_const_move (machine_mode mode, rtx dest, rtx src)
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riscv_emit_move (dest, src);
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}
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/* Report when we try to do something that requires vector when vector is
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disabled. This is an error of last resort and isn't very high-quality. It
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usually involves attempts to measure the vector length in some way. */
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static void
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riscv_report_v_required (void)
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{
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static bool reported_p = false;
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/* Avoid reporting a slew of messages for a single oversight. */
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if (reported_p)
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return;
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error ("this operation requires the RVV ISA extension");
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inform (input_location, "you can enable RVV using the command-line"
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" option %<-march%>, or by using the %<target%>"
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" attribute or pragma");
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reported_p = true;
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}
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/* Helper function to operation for rtx_code CODE. */
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static void
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riscv_expand_op (enum rtx_code code, machine_mode mode, rtx op0, rtx op1,
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rtx op2)
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{
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if (can_create_pseudo_p ())
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{
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rtx result;
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if (GET_RTX_CLASS (code) == RTX_UNARY)
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result = expand_simple_unop (mode, code, op1, NULL_RTX, false);
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else
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result = expand_simple_binop (mode, code, op1, op2, NULL_RTX, false,
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OPTAB_DIRECT);
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riscv_emit_move (op0, result);
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}
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else
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{
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rtx pat;
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/* The following implementation is for prologue and epilogue.
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Because prologue and epilogue can not use pseudo register.
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We can't using expand_simple_binop or expand_simple_unop. */
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if (GET_RTX_CLASS (code) == RTX_UNARY)
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pat = gen_rtx_fmt_e (code, mode, op1);
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else
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pat = gen_rtx_fmt_ee (code, mode, op1, op2);
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emit_insn (gen_rtx_SET (op0, pat));
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}
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}
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/* Expand mult operation with constant integer, multiplicand also used as a
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* temporary register. */
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static void
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riscv_expand_mult_with_const_int (machine_mode mode, rtx dest, rtx multiplicand,
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int multiplier)
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{
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if (multiplier == 0)
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{
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riscv_emit_move (dest, GEN_INT (0));
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return;
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}
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bool neg_p = multiplier < 0;
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int multiplier_abs = abs (multiplier);
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if (multiplier_abs == 1)
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{
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if (neg_p)
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riscv_expand_op (NEG, mode, dest, multiplicand, NULL_RTX);
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else
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riscv_emit_move (dest, multiplicand);
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}
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else
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{
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if (pow2p_hwi (multiplier_abs))
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{
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/*
|
||||
multiplicand = [BYTES_PER_RISCV_VECTOR].
|
||||
1. const_poly_int:P [BYTES_PER_RISCV_VECTOR * 8].
|
||||
Sequence:
|
||||
csrr a5, vlenb
|
||||
slli a5, a5, 3
|
||||
2. const_poly_int:P [-BYTES_PER_RISCV_VECTOR * 8].
|
||||
Sequence:
|
||||
csrr a5, vlenb
|
||||
slli a5, a5, 3
|
||||
neg a5, a5
|
||||
*/
|
||||
riscv_expand_op (ASHIFT, mode, dest, multiplicand,
|
||||
gen_int_mode (exact_log2 (multiplier_abs), QImode));
|
||||
if (neg_p)
|
||||
riscv_expand_op (NEG, mode, dest, dest, NULL_RTX);
|
||||
}
|
||||
else if (pow2p_hwi (multiplier_abs + 1))
|
||||
{
|
||||
/*
|
||||
multiplicand = [BYTES_PER_RISCV_VECTOR].
|
||||
1. const_poly_int:P [BYTES_PER_RISCV_VECTOR * 7].
|
||||
Sequence:
|
||||
csrr a5, vlenb
|
||||
slli a4, a5, 3
|
||||
sub a5, a4, a5
|
||||
2. const_poly_int:P [-BYTES_PER_RISCV_VECTOR * 7].
|
||||
Sequence:
|
||||
csrr a5, vlenb
|
||||
slli a4, a5, 3
|
||||
sub a5, a4, a5 + neg a5, a5 => sub a5, a5, a4
|
||||
*/
|
||||
riscv_expand_op (ASHIFT, mode, dest, multiplicand,
|
||||
gen_int_mode (exact_log2 (multiplier_abs + 1),
|
||||
QImode));
|
||||
if (neg_p)
|
||||
riscv_expand_op (MINUS, mode, dest, multiplicand, dest);
|
||||
else
|
||||
riscv_expand_op (MINUS, mode, dest, dest, multiplicand);
|
||||
}
|
||||
else if (pow2p_hwi (multiplier - 1))
|
||||
{
|
||||
/*
|
||||
multiplicand = [BYTES_PER_RISCV_VECTOR].
|
||||
1. const_poly_int:P [BYTES_PER_RISCV_VECTOR * 9].
|
||||
Sequence:
|
||||
csrr a5, vlenb
|
||||
slli a4, a5, 3
|
||||
add a5, a4, a5
|
||||
2. const_poly_int:P [-BYTES_PER_RISCV_VECTOR * 9].
|
||||
Sequence:
|
||||
csrr a5, vlenb
|
||||
slli a4, a5, 3
|
||||
add a5, a4, a5
|
||||
neg a5, a5
|
||||
*/
|
||||
riscv_expand_op (ASHIFT, mode, dest, multiplicand,
|
||||
gen_int_mode (exact_log2 (multiplier_abs - 1),
|
||||
QImode));
|
||||
riscv_expand_op (PLUS, mode, dest, dest, multiplicand);
|
||||
if (neg_p)
|
||||
riscv_expand_op (NEG, mode, dest, dest, NULL_RTX);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* We use multiplication for remaining cases. */
|
||||
gcc_assert (
|
||||
TARGET_MUL
|
||||
&& "M-extension must be enabled to calculate the poly_int "
|
||||
"size/offset.");
|
||||
riscv_emit_move (dest, gen_int_mode (multiplier, mode));
|
||||
riscv_expand_op (MULT, mode, dest, dest, multiplicand);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Analyze src and emit const_poly_int mov sequence. */
|
||||
|
||||
static void
|
||||
riscv_legitimize_poly_move (machine_mode mode, rtx dest, rtx tmp, rtx src)
|
||||
{
|
||||
poly_int64 value = rtx_to_poly_int64 (src);
|
||||
int offset = value.coeffs[0];
|
||||
int factor = value.coeffs[1];
|
||||
int vlenb = BYTES_PER_RISCV_VECTOR.coeffs[1];
|
||||
int div_factor = 0;
|
||||
/* Calculate (const_poly_int:MODE [m, n]) using scalar instructions.
|
||||
For any (const_poly_int:MODE [m, n]), the calculation formula is as
|
||||
follows.
|
||||
constant = m - n.
|
||||
When minimum VLEN = 32, poly of VLENB = (4, 4).
|
||||
base = vlenb(4, 4) or vlenb/2(2, 2) or vlenb/4(1, 1).
|
||||
When minimum VLEN > 32, poly of VLENB = (8, 8).
|
||||
base = vlenb(8, 8) or vlenb/2(4, 4) or vlenb/4(2, 2) or vlenb/8(1, 1).
|
||||
magn = (n, n) / base.
|
||||
(m, n) = base * magn + constant.
|
||||
This calculation doesn't need div operation. */
|
||||
|
||||
emit_move_insn (tmp, gen_int_mode (BYTES_PER_RISCV_VECTOR, mode));
|
||||
|
||||
if (BYTES_PER_RISCV_VECTOR.is_constant ())
|
||||
{
|
||||
gcc_assert (value.is_constant ());
|
||||
riscv_emit_move (dest, GEN_INT (value.to_constant ()));
|
||||
return;
|
||||
}
|
||||
else if ((factor % vlenb) == 0)
|
||||
div_factor = 1;
|
||||
else if ((factor % (vlenb / 2)) == 0)
|
||||
div_factor = 2;
|
||||
else if ((factor % (vlenb / 4)) == 0)
|
||||
div_factor = 4;
|
||||
else if ((factor % (vlenb / 8)) == 0)
|
||||
div_factor = 8;
|
||||
else
|
||||
gcc_unreachable ();
|
||||
|
||||
if (div_factor != 1)
|
||||
riscv_expand_op (LSHIFTRT, mode, tmp, tmp,
|
||||
gen_int_mode (exact_log2 (div_factor), QImode));
|
||||
|
||||
riscv_expand_mult_with_const_int (mode, dest, tmp,
|
||||
factor / (vlenb / div_factor));
|
||||
HOST_WIDE_INT constant = offset - factor;
|
||||
|
||||
if (constant == 0)
|
||||
return;
|
||||
else if (SMALL_OPERAND (constant))
|
||||
riscv_expand_op (PLUS, mode, dest, dest, gen_int_mode (constant, mode));
|
||||
else
|
||||
{
|
||||
/* Handle the constant value is not a 12-bit value. */
|
||||
rtx high;
|
||||
|
||||
/* Leave OFFSET as a 16-bit offset and put the excess in HIGH.
|
||||
The addition inside the macro CONST_HIGH_PART may cause an
|
||||
overflow, so we need to force a sign-extension check. */
|
||||
high = gen_int_mode (CONST_HIGH_PART (constant), mode);
|
||||
constant = CONST_LOW_PART (constant);
|
||||
riscv_emit_move (tmp, high);
|
||||
riscv_expand_op (PLUS, mode, dest, tmp, dest);
|
||||
riscv_expand_op (PLUS, mode, dest, dest, gen_int_mode (constant, mode));
|
||||
}
|
||||
}
|
||||
|
||||
/* If (set DEST SRC) is not a valid move instruction, emit an equivalent
|
||||
sequence that is valid. */
|
||||
|
||||
bool
|
||||
riscv_legitimize_move (machine_mode mode, rtx dest, rtx src)
|
||||
{
|
||||
if (CONST_POLY_INT_P (src))
|
||||
{
|
||||
poly_int64 value = rtx_to_poly_int64 (src);
|
||||
if (!value.is_constant () && !TARGET_VECTOR)
|
||||
{
|
||||
riscv_report_v_required ();
|
||||
return false;
|
||||
}
|
||||
|
||||
if (satisfies_constraint_vp (src))
|
||||
return false;
|
||||
|
||||
if (GET_MODE_SIZE (mode).to_constant () < GET_MODE_SIZE (Pmode))
|
||||
{
|
||||
/* In RV32 system, handle (const_poly_int:QI [m, n])
|
||||
(const_poly_int:HI [m, n]).
|
||||
In RV64 system, handle (const_poly_int:QI [m, n])
|
||||
(const_poly_int:HI [m, n])
|
||||
(const_poly_int:SI [m, n]). */
|
||||
rtx tmp = gen_reg_rtx (Pmode);
|
||||
riscv_legitimize_poly_move (Pmode, gen_lowpart (Pmode, dest), tmp,
|
||||
src);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* In RV32 system, handle (const_poly_int:SI [m, n])
|
||||
(const_poly_int:DI [m, n]).
|
||||
In RV64 system, handle (const_poly_int:DI [m, n]).
|
||||
FIXME: Maybe we could gen SImode in RV32 and then sign-extend to DImode,
|
||||
the offset should not exceed 4GiB in general. */
|
||||
rtx tmp = gen_reg_rtx (mode);
|
||||
riscv_legitimize_poly_move (mode, dest, tmp, src);
|
||||
}
|
||||
return true;
|
||||
}
|
||||
/* Expand
|
||||
(set (reg:QI target) (mem:QI (address)))
|
||||
to
|
||||
|
|
@ -5033,6 +5297,9 @@ riscv_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
|
|||
if (!riscv_v_ext_vector_mode_p (mode))
|
||||
return false;
|
||||
|
||||
if (!V_REG_P (regno + nregs - 1))
|
||||
return false;
|
||||
|
||||
/* 3.3.2. LMUL = 2,4,8, register numbers should be multiple of 2,4,8.
|
||||
but for mask vector register, register numbers can be any number. */
|
||||
int lmul = 1;
|
||||
|
|
@ -5041,6 +5308,8 @@ riscv_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
|
|||
if (lmul != 1)
|
||||
return ((regno % lmul) == 0);
|
||||
}
|
||||
else if (regno == VL_REGNUM || regno == VTYPE_REGNUM)
|
||||
return true;
|
||||
else
|
||||
return false;
|
||||
|
||||
|
|
@ -5231,10 +5500,6 @@ riscv_init_machine_status (void)
|
|||
static poly_uint16
|
||||
riscv_convert_vector_bits (void)
|
||||
{
|
||||
/* The runtime invariant is only meaningful when TARGET_VECTOR is enabled. */
|
||||
if (!TARGET_VECTOR)
|
||||
return 0;
|
||||
|
||||
if (TARGET_MIN_VLEN > 32)
|
||||
{
|
||||
/* When targetting minimum VLEN > 32, we should use 64-bit chunk size.
|
||||
|
|
@ -5255,7 +5520,13 @@ riscv_convert_vector_bits (void)
|
|||
riscv_bytes_per_vector_chunk = 4;
|
||||
}
|
||||
|
||||
return poly_uint16 (1, 1);
|
||||
/* Set riscv_vector_chunks as poly (1, 1) run-time constant if TARGET_VECTOR
|
||||
is enabled. Set riscv_vector_chunks as 1 compile-time constant if
|
||||
TARGET_VECTOR is disabled. riscv_vector_chunks is used in "riscv-modes.def"
|
||||
to set RVV mode size. The RVV machine modes size are run-time constant if
|
||||
TARGET_VECTOR is enabled. The RVV machine modes size remains default
|
||||
compile-time constant if TARGET_VECTOR is disabled. */
|
||||
return TARGET_VECTOR ? poly_uint16 (1, 1) : 1;
|
||||
}
|
||||
|
||||
/* Implement TARGET_OPTION_OVERRIDE. */
|
||||
|
|
@ -6002,6 +6273,23 @@ riscv_init_libfuncs (void)
|
|||
set_optab_libfunc (unord_optab, HFmode, NULL);
|
||||
}
|
||||
|
||||
#if CHECKING_P
|
||||
void
|
||||
riscv_reinit (void)
|
||||
{
|
||||
riscv_option_override ();
|
||||
init_adjust_machine_modes ();
|
||||
init_derived_machine_modes ();
|
||||
reinit_regs ();
|
||||
init_optabs ();
|
||||
}
|
||||
#endif
|
||||
|
||||
#if CHECKING_P
|
||||
#undef TARGET_RUN_TARGET_SELFTESTS
|
||||
#define TARGET_RUN_TARGET_SELFTESTS selftest::riscv_run_selftests
|
||||
#endif /* #if CHECKING_P */
|
||||
|
||||
/* Initialize the GCC target structure. */
|
||||
#undef TARGET_ASM_ALIGNED_HI_OP
|
||||
#define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
|
||||
|
|
|
|||
|
|
@ -23,6 +23,10 @@ riscv-shorten-memrefs.o: $(srcdir)/config/riscv/riscv-shorten-memrefs.cc
|
|||
$(COMPILE) $<
|
||||
$(POSTCOMPILE)
|
||||
|
||||
riscv-selftests.o: $(srcdir)/config/riscv/riscv-selftests.cc
|
||||
$(COMPILE) $<
|
||||
$(POSTCOMPILE)
|
||||
|
||||
PASSES_EXTRA += $(srcdir)/config/riscv/riscv-passes.def
|
||||
|
||||
$(common_out_file): $(srcdir)/config/riscv/riscv-cores.def \
|
||||
|
|
|
|||
8
gcc/testsuite/selftests/riscv/empty-func.rtl
Normal file
8
gcc/testsuite/selftests/riscv/empty-func.rtl
Normal file
|
|
@ -0,0 +1,8 @@
|
|||
(function "func"
|
||||
(insn-chain
|
||||
(block 2
|
||||
(edge-from entry (flags "FALLTHRU"))
|
||||
(edge-to exit (flags "FALLTHRU"))
|
||||
) ;; block 2
|
||||
) ;; insn-chain
|
||||
) ;; function
|
||||
Loading…
Add table
Reference in a new issue