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AArch64: correct constraint on Upl early clobber alternatives

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I made an oversight in the previous patch, where I added a ?Upa
alternative to the Upl cases.  This causes it to create the tie
between the larger register file rather than the constrained one.

This fixes the affected patterns.

gcc/ChangeLog:

	* config/aarch64/aarch64-sve.md (@aarch64_pred_cmp<cmp_op><mode>,
	*cmp<cmp_op><mode>_cc, *cmp<cmp_op><mode>_ptest,
	@aarch64_pred_cmp<cmp_op><mode>_wide,
	*aarch64_pred_cmp<cmp_op><mode>_wide_cc,
	*aarch64_pred_cmp<cmp_op><mode>_wide_ptest): Fix Upl tie alternative.
	* config/aarch64/aarch64-sve2.md (@aarch64_pred_<sve_int_op><mode>): Fix
	Upl tie alternative.
This commit is contained in:
Tamar Christina 2024-06-06 14:35:48 +01:00
parent 3a4775d440
commit afe85f8e22
2 changed files with 33 additions and 33 deletions
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64
gcc/config/aarch64/aarch64-sve.md
View file

@ -8134,13 +8134,13 @@
UNSPEC_PRED_Z))
(clobber (reg:CC_NZC CC_REGNUM))]
"TARGET_SVE"
{@ [ cons: =0 , 1 , 3 , 4 ; attrs: pred_clobber ]
[ &Upa , Upl , w , <sve_imm_con>; yes ] cmp<cmp_op>\t%0.<Vetype>, %1/z, %3.<Vetype>, #%4
[ ?Upa , 0Upl, w , <sve_imm_con>; yes ] ^
[ Upa , Upl , w , <sve_imm_con>; no ] ^
[ &Upa , Upl , w , w ; yes ] cmp<cmp_op>\t%0.<Vetype>, %1/z, %3.<Vetype>, %4.<Vetype>
[ ?Upa , 0Upl, w , w ; yes ] ^
[ Upa , Upl , w , w ; no ] ^
{@ [ cons: =0 , 1 , 3 , 4 ; attrs: pred_clobber ]
[ &Upa , Upl, w , <sve_imm_con>; yes ] cmp<cmp_op>\t%0.<Vetype>, %1/z, %3.<Vetype>, #%4
[ ?Upl , 0 , w , <sve_imm_con>; yes ] ^
[ Upa , Upl, w , <sve_imm_con>; no ] ^
[ &Upa , Upl, w , w ; yes ] cmp<cmp_op>\t%0.<Vetype>, %1/z, %3.<Vetype>, %4.<Vetype>
[ ?Upl , 0 , w , w ; yes ] ^
[ Upa , Upl, w , w ; no ] ^
}
)
@ -8170,13 +8170,13 @@
UNSPEC_PRED_Z))]
"TARGET_SVE
&& aarch64_sve_same_pred_for_ptest_p (&operands[4], &operands[6])"
{@ [ cons: =0 , 1 , 2 , 3 ; attrs: pred_clobber ]
[ &Upa , Upl , w , <sve_imm_con>; yes ] cmp<cmp_op>\t%0.<Vetype>, %1/z, %2.<Vetype>, #%3
[ ?Upa , 0Upl, w , <sve_imm_con>; yes ] ^
[ Upa , Upl , w , <sve_imm_con>; no ] ^
[ &Upa , Upl , w , w ; yes ] cmp<cmp_op>\t%0.<Vetype>, %1/z, %2.<Vetype>, %3.<Vetype>
[ ?Upa , 0Upl, w , w ; yes ] ^
[ Upa , Upl , w , w ; no ] ^
{@ [ cons: =0 , 1 , 2 , 3 ; attrs: pred_clobber ]
[ &Upa , Upl, w , <sve_imm_con>; yes ] cmp<cmp_op>\t%0.<Vetype>, %1/z, %2.<Vetype>, #%3
[ ?Upl , 0 , w , <sve_imm_con>; yes ] ^
[ Upa , Upl, w , <sve_imm_con>; no ] ^
[ &Upa , Upl, w , w ; yes ] cmp<cmp_op>\t%0.<Vetype>, %1/z, %2.<Vetype>, %3.<Vetype>
[ ?Upl , 0 , w , w ; yes ] ^
[ Upa , Upl, w , w ; no ] ^
}
"&& !rtx_equal_p (operands[4], operands[6])"
{
@ -8205,12 +8205,12 @@
"TARGET_SVE
&& aarch64_sve_same_pred_for_ptest_p (&operands[4], &operands[6])"
{@ [ cons: =0, 1 , 2 , 3 ; attrs: pred_clobber ]
[ &Upa , Upl , w , <sve_imm_con>; yes ] cmp<cmp_op>\t%0.<Vetype>, %1/z, %2.<Vetype>, #%3
[ ?Upa , 0Upl, w , <sve_imm_con>; yes ] ^
[ Upa , Upl , w , <sve_imm_con>; no ] ^
[ &Upa , Upl , w , w ; yes ] cmp<cmp_op>\t%0.<Vetype>, %1/z, %2.<Vetype>, %3.<Vetype>
[ ?Upa , 0Upl, w , w ; yes ] ^
[ Upa , Upl , w , w ; no ] ^
[ &Upa , Upl, w , <sve_imm_con>; yes ] cmp<cmp_op>\t%0.<Vetype>, %1/z, %2.<Vetype>, #%3
[ ?Upl , 0 , w , <sve_imm_con>; yes ] ^
[ Upa , Upl, w , <sve_imm_con>; no ] ^
[ &Upa , Upl, w , w ; yes ] cmp<cmp_op>\t%0.<Vetype>, %1/z, %2.<Vetype>, %3.<Vetype>
[ ?Upl , 0 , w , w ; yes ] ^
[ Upa , Upl, w , w ; no ] ^
}
"&& !rtx_equal_p (operands[4], operands[6])"
{
@ -8263,10 +8263,10 @@
UNSPEC_PRED_Z))
(clobber (reg:CC_NZC CC_REGNUM))]
"TARGET_SVE"
{@ [ cons: =0, 1 , 2, 3, 4; attrs: pred_clobber ]
[ &Upa , Upl , , w, w; yes ] cmp<cmp_op>\t%0.<Vetype>, %1/z, %3.<Vetype>, %4.d
[ ?Upa , 0Upl, , w, w; yes ] ^
[ Upa , Upl , , w, w; no ] ^
{@ [ cons: =0, 1 , 2, 3, 4; attrs: pred_clobber ]
[ &Upa , Upl, , w, w; yes ] cmp<cmp_op>\t%0.<Vetype>, %1/z, %3.<Vetype>, %4.d
[ ?Upl , 0 , , w, w; yes ] ^
[ Upa , Upl, , w, w; no ] ^
}
)
@ -8298,10 +8298,10 @@
UNSPEC_PRED_Z))]
"TARGET_SVE
&& aarch64_sve_same_pred_for_ptest_p (&operands[4], &operands[6])"
{@ [ cons: =0, 1 , 2, 3, 6 ; attrs: pred_clobber ]
[ &Upa , Upl , w, w, Upl; yes ] cmp<cmp_op>\t%0.<Vetype>, %1/z, %2.<Vetype>, %3.d
[ ?Upa , 0Upl, w, w, Upl; yes ] ^
[ Upa , Upl , w, w, Upl; no ] ^
{@ [ cons: =0, 1 , 2, 3, 6 ; attrs: pred_clobber ]
[ &Upa , Upl, w, w, Upl; yes ] cmp<cmp_op>\t%0.<Vetype>, %1/z, %2.<Vetype>, %3.d
[ ?Upl , 0 , w, w, Upl; yes ] ^
[ Upa , Upl, w, w, Upl; no ] ^
}
)
@ -8325,10 +8325,10 @@
(clobber (match_scratch:<VPRED> 0))]
"TARGET_SVE
&& aarch64_sve_same_pred_for_ptest_p (&operands[4], &operands[6])"
{@ [ cons: =0, 1 , 2, 3, 6 ; attrs: pred_clobber ]
[ &Upa , Upl , w, w, Upl; yes ] cmp<cmp_op>\t%0.<Vetype>, %1/z, %2.<Vetype>, %3.d
[ ?Upa , 0Upl, w, w, Upl; yes ] ^
[ Upa , Upl , w, w, Upl; no ] ^
{@ [ cons: =0, 1 , 2, 3, 6 ; attrs: pred_clobber ]
[ &Upa , Upl, w, w, Upl; yes ] cmp<cmp_op>\t%0.<Vetype>, %1/z, %2.<Vetype>, %3.d
[ ?Upl , 0 , w, w, Upl; yes ] ^
[ Upa , Upl, w, w, Upl; no ] ^
}
)

2
gcc/config/aarch64/aarch64-sve2.md
View file

@ -3351,7 +3351,7 @@
"TARGET_SVE2 && TARGET_NON_STREAMING"
{@ [ cons: =0, 1 , 3, 4; attrs: pred_clobber ]
[ &Upa , Upl, w, w; yes ] <sve_int_op>\t%0.<Vetype>, %1/z, %3.<Vetype>, %4.<Vetype>
[ ?Upa , 0 , w, w; yes ] ^
[ ?Upl , 0 , w, w; yes ] ^
[ Upa , Upl, w, w; no ] ^
}
)