From afe85f8e22a703280b17c701f3490d89337f674a Mon Sep 17 00:00:00 2001 From: Tamar Christina Date: Thu, 6 Jun 2024 14:35:48 +0100 Subject: [PATCH] AArch64: correct constraint on Upl early clobber alternatives I made an oversight in the previous patch, where I added a ?Upa alternative to the Upl cases. This causes it to create the tie between the larger register file rather than the constrained one. This fixes the affected patterns. gcc/ChangeLog: * config/aarch64/aarch64-sve.md (@aarch64_pred_cmp, *cmp_cc, *cmp_ptest, @aarch64_pred_cmp_wide, *aarch64_pred_cmp_wide_cc, *aarch64_pred_cmp_wide_ptest): Fix Upl tie alternative. * config/aarch64/aarch64-sve2.md (@aarch64_pred_): Fix Upl tie alternative. --- gcc/config/aarch64/aarch64-sve.md | 64 +++++++++++++++--------------- gcc/config/aarch64/aarch64-sve2.md | 2 +- 2 files changed, 33 insertions(+), 33 deletions(-) diff --git a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64-sve.md index d902bce62fd..d69db34016a 100644 --- a/gcc/config/aarch64/aarch64-sve.md +++ b/gcc/config/aarch64/aarch64-sve.md @@ -8134,13 +8134,13 @@ UNSPEC_PRED_Z)) (clobber (reg:CC_NZC CC_REGNUM))] "TARGET_SVE" - {@ [ cons: =0 , 1 , 3 , 4 ; attrs: pred_clobber ] - [ &Upa , Upl , w , ; yes ] cmp\t%0., %1/z, %3., #%4 - [ ?Upa , 0Upl, w , ; yes ] ^ - [ Upa , Upl , w , ; no ] ^ - [ &Upa , Upl , w , w ; yes ] cmp\t%0., %1/z, %3., %4. - [ ?Upa , 0Upl, w , w ; yes ] ^ - [ Upa , Upl , w , w ; no ] ^ + {@ [ cons: =0 , 1 , 3 , 4 ; attrs: pred_clobber ] + [ &Upa , Upl, w , ; yes ] cmp\t%0., %1/z, %3., #%4 + [ ?Upl , 0 , w , ; yes ] ^ + [ Upa , Upl, w , ; no ] ^ + [ &Upa , Upl, w , w ; yes ] cmp\t%0., %1/z, %3., %4. + [ ?Upl , 0 , w , w ; yes ] ^ + [ Upa , Upl, w , w ; no ] ^ } ) @@ -8170,13 +8170,13 @@ UNSPEC_PRED_Z))] "TARGET_SVE && aarch64_sve_same_pred_for_ptest_p (&operands[4], &operands[6])" - {@ [ cons: =0 , 1 , 2 , 3 ; attrs: pred_clobber ] - [ &Upa , Upl , w , ; yes ] cmp\t%0., %1/z, %2., #%3 - [ ?Upa , 0Upl, w , ; yes ] ^ - [ Upa , Upl , w , ; no ] ^ - [ &Upa , Upl , w , w ; yes ] cmp\t%0., %1/z, %2., %3. - [ ?Upa , 0Upl, w , w ; yes ] ^ - [ Upa , Upl , w , w ; no ] ^ + {@ [ cons: =0 , 1 , 2 , 3 ; attrs: pred_clobber ] + [ &Upa , Upl, w , ; yes ] cmp\t%0., %1/z, %2., #%3 + [ ?Upl , 0 , w , ; yes ] ^ + [ Upa , Upl, w , ; no ] ^ + [ &Upa , Upl, w , w ; yes ] cmp\t%0., %1/z, %2., %3. + [ ?Upl , 0 , w , w ; yes ] ^ + [ Upa , Upl, w , w ; no ] ^ } "&& !rtx_equal_p (operands[4], operands[6])" { @@ -8205,12 +8205,12 @@ "TARGET_SVE && aarch64_sve_same_pred_for_ptest_p (&operands[4], &operands[6])" {@ [ cons: =0, 1 , 2 , 3 ; attrs: pred_clobber ] - [ &Upa , Upl , w , ; yes ] cmp\t%0., %1/z, %2., #%3 - [ ?Upa , 0Upl, w , ; yes ] ^ - [ Upa , Upl , w , ; no ] ^ - [ &Upa , Upl , w , w ; yes ] cmp\t%0., %1/z, %2., %3. - [ ?Upa , 0Upl, w , w ; yes ] ^ - [ Upa , Upl , w , w ; no ] ^ + [ &Upa , Upl, w , ; yes ] cmp\t%0., %1/z, %2., #%3 + [ ?Upl , 0 , w , ; yes ] ^ + [ Upa , Upl, w , ; no ] ^ + [ &Upa , Upl, w , w ; yes ] cmp\t%0., %1/z, %2., %3. + [ ?Upl , 0 , w , w ; yes ] ^ + [ Upa , Upl, w , w ; no ] ^ } "&& !rtx_equal_p (operands[4], operands[6])" { @@ -8263,10 +8263,10 @@ UNSPEC_PRED_Z)) (clobber (reg:CC_NZC CC_REGNUM))] "TARGET_SVE" - {@ [ cons: =0, 1 , 2, 3, 4; attrs: pred_clobber ] - [ &Upa , Upl , , w, w; yes ] cmp\t%0., %1/z, %3., %4.d - [ ?Upa , 0Upl, , w, w; yes ] ^ - [ Upa , Upl , , w, w; no ] ^ + {@ [ cons: =0, 1 , 2, 3, 4; attrs: pred_clobber ] + [ &Upa , Upl, , w, w; yes ] cmp\t%0., %1/z, %3., %4.d + [ ?Upl , 0 , , w, w; yes ] ^ + [ Upa , Upl, , w, w; no ] ^ } ) @@ -8298,10 +8298,10 @@ UNSPEC_PRED_Z))] "TARGET_SVE && aarch64_sve_same_pred_for_ptest_p (&operands[4], &operands[6])" - {@ [ cons: =0, 1 , 2, 3, 6 ; attrs: pred_clobber ] - [ &Upa , Upl , w, w, Upl; yes ] cmp\t%0., %1/z, %2., %3.d - [ ?Upa , 0Upl, w, w, Upl; yes ] ^ - [ Upa , Upl , w, w, Upl; no ] ^ + {@ [ cons: =0, 1 , 2, 3, 6 ; attrs: pred_clobber ] + [ &Upa , Upl, w, w, Upl; yes ] cmp\t%0., %1/z, %2., %3.d + [ ?Upl , 0 , w, w, Upl; yes ] ^ + [ Upa , Upl, w, w, Upl; no ] ^ } ) @@ -8325,10 +8325,10 @@ (clobber (match_scratch: 0))] "TARGET_SVE && aarch64_sve_same_pred_for_ptest_p (&operands[4], &operands[6])" - {@ [ cons: =0, 1 , 2, 3, 6 ; attrs: pred_clobber ] - [ &Upa , Upl , w, w, Upl; yes ] cmp\t%0., %1/z, %2., %3.d - [ ?Upa , 0Upl, w, w, Upl; yes ] ^ - [ Upa , Upl , w, w, Upl; no ] ^ + {@ [ cons: =0, 1 , 2, 3, 6 ; attrs: pred_clobber ] + [ &Upa , Upl, w, w, Upl; yes ] cmp\t%0., %1/z, %2., %3.d + [ ?Upl , 0 , w, w, Upl; yes ] ^ + [ Upa , Upl, w, w, Upl; no ] ^ } ) diff --git a/gcc/config/aarch64/aarch64-sve2.md b/gcc/config/aarch64/aarch64-sve2.md index eaba9d8f25f..972b03a4fef 100644 --- a/gcc/config/aarch64/aarch64-sve2.md +++ b/gcc/config/aarch64/aarch64-sve2.md @@ -3351,7 +3351,7 @@ "TARGET_SVE2 && TARGET_NON_STREAMING" {@ [ cons: =0, 1 , 3, 4; attrs: pred_clobber ] [ &Upa , Upl, w, w; yes ] \t%0., %1/z, %3., %4. - [ ?Upa , 0 , w, w; yes ] ^ + [ ?Upl , 0 , w, w; yes ] ^ [ Upa , Upl, w, w; no ] ^ } )