i386.c: Rename pni to sse3.
2004-02-23 Kelley Cook <kcook@gcc.gnu.org>
* config/i386/i386.c: Rename pni to sse3.
* config/i386/i386.h: Likewise.
* config/i386/i386.md: Likewise.
* config/i386/pmmintrin.h: Likewise.
* doc/extend.texi: Likewise.
* doc/invoke.texi: Likewise.
From-SVN: r78349
This commit is contained in:
Kelley Cook
H.J. Lu
parent
4a368ffd95
commit
9e200aafa5
7 changed files with 60 additions and 51 deletions
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@ -1,3 +1,12 @@
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2004-02-23 Kelley Cook <kcook@gcc.gnu.org>
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* config/i386/i386.c: Rename pni to sse3.
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* config/i386/i386.h: Likewise.
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* config/i386/i386.md: Likewise.
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* config/i386/pmmintrin.h: Likewise.
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* doc/extend.texi: Likewise.
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* doc/invoke.texi: Likewise.
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2004-02-23 Zack Weinberg <zack@codesourcery.com>
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Kazu Hirata <kazu@cs.umass.edu>
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@ -1391,8 +1391,8 @@ override_options (void)
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if (x86_arch_always_fancy_math_387 & (1 << ix86_arch))
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target_flags &= ~MASK_NO_FANCY_MATH_387;
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/* Turn on SSE2 builtins for -mpni. */
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if (TARGET_PNI)
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/* Turn on SSE2 builtins for -msse3. */
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if (TARGET_SSE3)
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target_flags |= MASK_SSE2;
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/* Turn on SSE builtins for -msse2. */
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@ -13072,13 +13072,13 @@ static const struct builtin_description bdesc_2arg[] =
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{ MASK_SSE2, CODE_FOR_cvtsd2ss, 0, IX86_BUILTIN_CVTSD2SS, 0, 0 },
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{ MASK_SSE2, CODE_FOR_cvtss2sd, 0, IX86_BUILTIN_CVTSS2SD, 0, 0 },
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/* PNI MMX */
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{ MASK_PNI, CODE_FOR_addsubv4sf3, "__builtin_ia32_addsubps", IX86_BUILTIN_ADDSUBPS, 0, 0 },
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{ MASK_PNI, CODE_FOR_addsubv2df3, "__builtin_ia32_addsubpd", IX86_BUILTIN_ADDSUBPD, 0, 0 },
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{ MASK_PNI, CODE_FOR_haddv4sf3, "__builtin_ia32_haddps", IX86_BUILTIN_HADDPS, 0, 0 },
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{ MASK_PNI, CODE_FOR_haddv2df3, "__builtin_ia32_haddpd", IX86_BUILTIN_HADDPD, 0, 0 },
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{ MASK_PNI, CODE_FOR_hsubv4sf3, "__builtin_ia32_hsubps", IX86_BUILTIN_HSUBPS, 0, 0 },
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{ MASK_PNI, CODE_FOR_hsubv2df3, "__builtin_ia32_hsubpd", IX86_BUILTIN_HSUBPD, 0, 0 }
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/* SSE3 MMX */
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{ MASK_SSE3, CODE_FOR_addsubv4sf3, "__builtin_ia32_addsubps", IX86_BUILTIN_ADDSUBPS, 0, 0 },
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{ MASK_SSE3, CODE_FOR_addsubv2df3, "__builtin_ia32_addsubpd", IX86_BUILTIN_ADDSUBPD, 0, 0 },
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{ MASK_SSE3, CODE_FOR_haddv4sf3, "__builtin_ia32_haddps", IX86_BUILTIN_HADDPS, 0, 0 },
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{ MASK_SSE3, CODE_FOR_haddv2df3, "__builtin_ia32_haddpd", IX86_BUILTIN_HADDPD, 0, 0 },
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{ MASK_SSE3, CODE_FOR_hsubv4sf3, "__builtin_ia32_hsubps", IX86_BUILTIN_HSUBPS, 0, 0 },
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{ MASK_SSE3, CODE_FOR_hsubv2df3, "__builtin_ia32_hsubpd", IX86_BUILTIN_HSUBPD, 0, 0 }
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};
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static const struct builtin_description bdesc_1arg[] =
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@ -13126,10 +13126,10 @@ static const struct builtin_description bdesc_1arg[] =
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{ MASK_SSE2, CODE_FOR_sse2_movq, 0, IX86_BUILTIN_MOVQ, 0, 0 },
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/* PNI */
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{ MASK_PNI, CODE_FOR_movshdup, 0, IX86_BUILTIN_MOVSHDUP, 0, 0 },
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{ MASK_PNI, CODE_FOR_movsldup, 0, IX86_BUILTIN_MOVSLDUP, 0, 0 },
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{ MASK_PNI, CODE_FOR_movddup, 0, IX86_BUILTIN_MOVDDUP, 0, 0 }
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/* SSE3 */
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{ MASK_SSE3, CODE_FOR_movshdup, 0, IX86_BUILTIN_MOVSHDUP, 0, 0 },
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{ MASK_SSE3, CODE_FOR_movsldup, 0, IX86_BUILTIN_MOVSLDUP, 0, 0 },
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{ MASK_SSE3, CODE_FOR_movddup, 0, IX86_BUILTIN_MOVDDUP, 0, 0 }
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};
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void
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@ -13755,23 +13755,23 @@ ix86_init_mmx_sse_builtins (void)
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def_builtin (MASK_SSE2, "__builtin_ia32_pmaddwd128", v4si_ftype_v8hi_v8hi, IX86_BUILTIN_PMADDWD128);
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/* Prescott New Instructions. */
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def_builtin (MASK_PNI, "__builtin_ia32_monitor",
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def_builtin (MASK_SSE3, "__builtin_ia32_monitor",
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void_ftype_pcvoid_unsigned_unsigned,
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IX86_BUILTIN_MONITOR);
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def_builtin (MASK_PNI, "__builtin_ia32_mwait",
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def_builtin (MASK_SSE3, "__builtin_ia32_mwait",
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void_ftype_unsigned_unsigned,
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IX86_BUILTIN_MWAIT);
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def_builtin (MASK_PNI, "__builtin_ia32_movshdup",
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def_builtin (MASK_SSE3, "__builtin_ia32_movshdup",
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v4sf_ftype_v4sf,
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IX86_BUILTIN_MOVSHDUP);
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def_builtin (MASK_PNI, "__builtin_ia32_movsldup",
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def_builtin (MASK_SSE3, "__builtin_ia32_movsldup",
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v4sf_ftype_v4sf,
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IX86_BUILTIN_MOVSLDUP);
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def_builtin (MASK_PNI, "__builtin_ia32_lddqu",
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def_builtin (MASK_SSE3, "__builtin_ia32_lddqu",
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v16qi_ftype_pcchar, IX86_BUILTIN_LDDQU);
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def_builtin (MASK_PNI, "__builtin_ia32_loadddup",
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def_builtin (MASK_SSE3, "__builtin_ia32_loadddup",
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v2df_ftype_pcdouble, IX86_BUILTIN_LOADDDUP);
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def_builtin (MASK_PNI, "__builtin_ia32_movddup",
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def_builtin (MASK_SSE3, "__builtin_ia32_movddup",
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v2df_ftype_v2df, IX86_BUILTIN_MOVDDUP);
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}
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@ -121,7 +121,7 @@ extern int target_flags;
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#define MASK_MMX 0x00002000 /* Support MMX regs/builtins */
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#define MASK_SSE 0x00004000 /* Support SSE regs/builtins */
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#define MASK_SSE2 0x00008000 /* Support SSE2 regs/builtins */
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#define MASK_PNI 0x00010000 /* Support PNI regs/builtins */
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#define MASK_SSE3 0x00010000 /* Support SSE3 regs/builtins */
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#define MASK_3DNOW 0x00020000 /* Support 3Dnow builtins */
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#define MASK_3DNOW_A 0x00040000 /* Support Athlon 3Dnow builtins */
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#define MASK_128BIT_LONG_DOUBLE 0x00080000 /* long double size is 128bit */
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@ -304,7 +304,7 @@ extern int x86_prefetch_sse;
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#define TARGET_SSE ((target_flags & MASK_SSE) != 0)
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#define TARGET_SSE2 ((target_flags & MASK_SSE2) != 0)
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#define TARGET_PNI ((target_flags & MASK_PNI) != 0)
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#define TARGET_SSE3 ((target_flags & MASK_SSE3) != 0)
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#define TARGET_SSE_MATH ((ix86_fpmath & FPMATH_SSE) != 0)
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#define TARGET_MIX_SSE_I387 ((ix86_fpmath & FPMATH_SSE) \
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&& (ix86_fpmath & FPMATH_387))
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@ -400,10 +400,10 @@ extern int x86_prefetch_sse;
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N_("Support MMX, SSE and SSE2 built-in functions and code generation") }, \
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{ "no-sse2", -MASK_SSE2, \
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N_("Do not support MMX, SSE and SSE2 built-in functions and code generation") }, \
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{ "pni", MASK_PNI, \
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N_("Support MMX, SSE, SSE2 and PNI built-in functions and code generation") },\
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{ "no-pni", -MASK_PNI, \
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N_("Do not support MMX, SSE, SSE2 and PNI built-in functions and code generation") },\
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{ "sse3", MASK_SSE3, \
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N_("Support MMX, SSE, SSE2 and SSE3 built-in functions and code generation") },\
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{ "no-sse3", -MASK_SSE3, \
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N_("Do not support MMX, SSE, SSE2 and SSE3 built-in functions and code generation") },\
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{ "128bit-long-double", MASK_128BIT_LONG_DOUBLE, \
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N_("sizeof(long double) is 16") }, \
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{ "96bit-long-double", -MASK_128BIT_LONG_DOUBLE, \
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@ -617,8 +617,8 @@ extern int x86_prefetch_sse;
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builtin_define ("__SSE__"); \
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if (TARGET_SSE2) \
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builtin_define ("__SSE2__"); \
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if (TARGET_PNI) \
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builtin_define ("__PNI__"); \
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if (TARGET_SSE3) \
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builtin_define ("__SSE3__"); \
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if (TARGET_SSE_MATH && TARGET_SSE) \
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builtin_define ("__SSE_MATH__"); \
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if (TARGET_SSE_MATH && TARGET_SSE2) \
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@ -22930,13 +22930,13 @@
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[(set_attr "type" "sse")
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(set_attr "memory" "unknown")])
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;; PNI
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;; SSE3
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(define_insn "mwait"
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[(unspec_volatile [(match_operand:SI 0 "register_operand" "a")
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(match_operand:SI 1 "register_operand" "c")]
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UNSPECV_MWAIT)]
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"TARGET_PNI"
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"TARGET_SSE3"
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"mwait\t%0, %1"
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[(set_attr "length" "3")])
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@ -22945,18 +22945,18 @@
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(match_operand:SI 1 "register_operand" "c")
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(match_operand:SI 2 "register_operand" "d")]
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UNSPECV_MONITOR)]
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"TARGET_PNI"
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"TARGET_SSE3"
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"monitor\t%0, %1, %2"
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[(set_attr "length" "3")])
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;; PNI arithmetic
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;; SSE3 arithmetic
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(define_insn "addsubv4sf3"
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[(set (match_operand:V4SF 0 "register_operand" "=x")
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(unspec:V4SF [(match_operand:V4SF 1 "register_operand" "0")
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(match_operand:V4SF 2 "nonimmediate_operand" "xm")]
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UNSPEC_ADDSUB))]
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"TARGET_PNI"
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"TARGET_SSE3"
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"addsubps\t{%2, %0|%0, %2}"
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[(set_attr "type" "sseadd")
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(set_attr "mode" "V4SF")])
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@ -22966,7 +22966,7 @@
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(unspec:V2DF [(match_operand:V2DF 1 "register_operand" "0")
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(match_operand:V2DF 2 "nonimmediate_operand" "xm")]
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UNSPEC_ADDSUB))]
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"TARGET_PNI"
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"TARGET_SSE3"
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"addsubpd\t{%2, %0|%0, %2}"
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[(set_attr "type" "sseadd")
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(set_attr "mode" "V2DF")])
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@ -22976,7 +22976,7 @@
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(unspec:V4SF [(match_operand:V4SF 1 "register_operand" "0")
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(match_operand:V4SF 2 "nonimmediate_operand" "xm")]
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UNSPEC_HADD))]
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"TARGET_PNI"
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"TARGET_SSE3"
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"haddps\t{%2, %0|%0, %2}"
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[(set_attr "type" "sseadd")
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(set_attr "mode" "V4SF")])
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@ -22986,7 +22986,7 @@
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(unspec:V2DF [(match_operand:V2DF 1 "register_operand" "0")
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(match_operand:V2DF 2 "nonimmediate_operand" "xm")]
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UNSPEC_HADD))]
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"TARGET_PNI"
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"TARGET_SSE3"
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"haddpd\t{%2, %0|%0, %2}"
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[(set_attr "type" "sseadd")
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(set_attr "mode" "V2DF")])
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@ -22996,7 +22996,7 @@
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(unspec:V4SF [(match_operand:V4SF 1 "register_operand" "0")
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(match_operand:V4SF 2 "nonimmediate_operand" "xm")]
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UNSPEC_HSUB))]
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"TARGET_PNI"
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"TARGET_SSE3"
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"hsubps\t{%2, %0|%0, %2}"
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[(set_attr "type" "sseadd")
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(set_attr "mode" "V4SF")])
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@ -23006,7 +23006,7 @@
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(unspec:V2DF [(match_operand:V2DF 1 "register_operand" "0")
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(match_operand:V2DF 2 "nonimmediate_operand" "xm")]
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UNSPEC_HSUB))]
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"TARGET_PNI"
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"TARGET_SSE3"
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"hsubpd\t{%2, %0|%0, %2}"
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[(set_attr "type" "sseadd")
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(set_attr "mode" "V2DF")])
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@ -23015,7 +23015,7 @@
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[(set (match_operand:V4SF 0 "register_operand" "=x")
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(unspec:V4SF
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[(match_operand:V4SF 1 "nonimmediate_operand" "xm")] UNSPEC_MOVSHDUP))]
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"TARGET_PNI"
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"TARGET_SSE3"
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"movshdup\t{%1, %0|%0, %1}"
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[(set_attr "type" "sse")
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(set_attr "mode" "V4SF")])
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@ -23024,7 +23024,7 @@
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[(set (match_operand:V4SF 0 "register_operand" "=x")
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(unspec:V4SF
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[(match_operand:V4SF 1 "nonimmediate_operand" "xm")] UNSPEC_MOVSLDUP))]
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"TARGET_PNI"
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"TARGET_SSE3"
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"movsldup\t{%1, %0|%0, %1}"
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[(set_attr "type" "sse")
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(set_attr "mode" "V4SF")])
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@ -23033,7 +23033,7 @@
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[(set (match_operand:V16QI 0 "register_operand" "=x")
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(unspec:V16QI [(match_operand:V16QI 1 "memory_operand" "m")]
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UNSPEC_LDQQU))]
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"TARGET_PNI"
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"TARGET_SSE3"
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"lddqu\t{%1, %0|%0, %1}"
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[(set_attr "type" "ssecvt")
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(set_attr "mode" "TI")])
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@ -23041,7 +23041,7 @@
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(define_insn "loadddup"
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[(set (match_operand:V2DF 0 "register_operand" "=x")
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(vec_duplicate:V2DF (match_operand:DF 1 "memory_operand" "m")))]
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"TARGET_PNI"
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"TARGET_SSE3"
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"movddup\t{%1, %0|%0, %1}"
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[(set_attr "type" "ssecvt")
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(set_attr "mode" "DF")])
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@ -23051,7 +23051,7 @@
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(vec_duplicate:V2DF
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(vec_select:DF (match_operand:V2DF 1 "register_operand" "x")
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(parallel [(const_int 0)]))))]
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"TARGET_PNI"
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"TARGET_SSE3"
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"movddup\t{%1, %0|%0, %1}"
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[(set_attr "type" "ssecvt")
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(set_attr "mode" "DF")])
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@ -30,7 +30,7 @@
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#ifndef _PMMINTRIN_H_INCLUDED
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#define _PMMINTRIN_H_INCLUDED
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#ifdef __PNI__
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#ifdef __SSE3__
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#include <xmmintrin.h>
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#include <emmintrin.h>
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@ -127,6 +127,6 @@ _mm_mwait (unsigned int __E, unsigned int __H)
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#define _mm_mwait(E, H) __builtin_ia32_mwait ((E), (H))
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#endif
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#endif /* __PNI__ */
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#endif /* __SSE3__ */
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#endif /* _PMMINTRIN_H_INCLUDED */
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@ -5977,7 +5977,7 @@ Generates the @code{movhps} machine instruction as a store to memory.
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Generates the @code{movlps} machine instruction as a store to memory.
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@end table
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The following built-in functions are available when @option{-mpni} is used.
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The following built-in functions are available when @option{-msse3} is used.
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All of them generate the machine instruction that is part of the name.
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@smallexample
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@ -5995,7 +5995,7 @@ v4sf __builtin_ia32_movsldup (v4sf)
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void __builtin_ia32_mwait (unsigned int, unsigned int)
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@end smallexample
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The following built-in functions are available when @option{-mpni} is used.
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The following built-in functions are available when @option{-msse3} is used.
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@table @code
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@item v2df __builtin_ia32_loadddup (double const *)
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@ -488,7 +488,7 @@ in the following sections.
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-mno-fp-ret-in-387 -msoft-float -msvr3-shlib @gol
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-mno-wide-multiply -mrtd -malign-double @gol
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-mpreferred-stack-boundary=@var{num} @gol
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-mmmx -msse -msse2 -mpni -m3dnow @gol
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-mmmx -msse -msse2 -msse3 -m3dnow @gol
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-mthreads -mno-align-stringops -minline-all-stringops @gol
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-mpush-args -maccumulate-outgoing-args -m128bit-long-double @gol
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-m96bit-long-double -mregparm=@var{num} -momit-leaf-frame-pointer @gol
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@ -8385,8 +8385,8 @@ preferred alignment to @option{-mpreferred-stack-boundary=2}.
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@itemx -mno-sse
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@item -msse2
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@itemx -mno-sse2
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@item -mpni
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@itemx -mno-pni
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@item -msse3
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@itemx -mno-sse3
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@item -m3dnow
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@itemx -mno-3dnow
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@opindex mmmx
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@ -8396,7 +8396,7 @@ preferred alignment to @option{-mpreferred-stack-boundary=2}.
|
|||
@opindex m3dnow
|
||||
@opindex mno-3dnow
|
||||
These switches enable or disable the use of built-in functions that allow
|
||||
direct access to the MMX, SSE, SSE2, PNI and 3Dnow extensions of the
|
||||
direct access to the MMX, SSE, SSE2, SSE3 and 3Dnow extensions of the
|
||||
instruction set.
|
||||
|
||||
@xref{X86 Built-in Functions}, for details of the functions enabled
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue