From 9e200aafa53204e1c556d82ee4ab8198ad5da48c Mon Sep 17 00:00:00 2001 From: Kelley Cook Date: Tue, 24 Feb 2004 03:27:11 +0000 Subject: [PATCH] i386.c: Rename pni to sse3. 2004-02-23 Kelley Cook * config/i386/i386.c: Rename pni to sse3. * config/i386/i386.h: Likewise. * config/i386/i386.md: Likewise. * config/i386/pmmintrin.h: Likewise. * doc/extend.texi: Likewise. * doc/invoke.texi: Likewise. From-SVN: r78349 --- gcc/ChangeLog | 9 +++++++++ gcc/config/i386/i386.c | 40 ++++++++++++++++++------------------- gcc/config/i386/i386.h | 16 +++++++-------- gcc/config/i386/i386.md | 30 ++++++++++++++-------------- gcc/config/i386/pmmintrin.h | 4 ++-- gcc/doc/extend.texi | 4 ++-- gcc/doc/invoke.texi | 8 ++++---- 7 files changed, 60 insertions(+), 51 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 79cf6b0ebf8..73349383a33 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,12 @@ +2004-02-23 Kelley Cook + + * config/i386/i386.c: Rename pni to sse3. + * config/i386/i386.h: Likewise. + * config/i386/i386.md: Likewise. + * config/i386/pmmintrin.h: Likewise. + * doc/extend.texi: Likewise. + * doc/invoke.texi: Likewise. + 2004-02-23 Zack Weinberg Kazu Hirata diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 92d56a004a0..02f62f4e74e 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -1391,8 +1391,8 @@ override_options (void) if (x86_arch_always_fancy_math_387 & (1 << ix86_arch)) target_flags &= ~MASK_NO_FANCY_MATH_387; - /* Turn on SSE2 builtins for -mpni. */ - if (TARGET_PNI) + /* Turn on SSE2 builtins for -msse3. */ + if (TARGET_SSE3) target_flags |= MASK_SSE2; /* Turn on SSE builtins for -msse2. */ @@ -13072,13 +13072,13 @@ static const struct builtin_description bdesc_2arg[] = { MASK_SSE2, CODE_FOR_cvtsd2ss, 0, IX86_BUILTIN_CVTSD2SS, 0, 0 }, { MASK_SSE2, CODE_FOR_cvtss2sd, 0, IX86_BUILTIN_CVTSS2SD, 0, 0 }, - /* PNI MMX */ - { MASK_PNI, CODE_FOR_addsubv4sf3, "__builtin_ia32_addsubps", IX86_BUILTIN_ADDSUBPS, 0, 0 }, - { MASK_PNI, CODE_FOR_addsubv2df3, "__builtin_ia32_addsubpd", IX86_BUILTIN_ADDSUBPD, 0, 0 }, - { MASK_PNI, CODE_FOR_haddv4sf3, "__builtin_ia32_haddps", IX86_BUILTIN_HADDPS, 0, 0 }, - { MASK_PNI, CODE_FOR_haddv2df3, "__builtin_ia32_haddpd", IX86_BUILTIN_HADDPD, 0, 0 }, - { MASK_PNI, CODE_FOR_hsubv4sf3, "__builtin_ia32_hsubps", IX86_BUILTIN_HSUBPS, 0, 0 }, - { MASK_PNI, CODE_FOR_hsubv2df3, "__builtin_ia32_hsubpd", IX86_BUILTIN_HSUBPD, 0, 0 } + /* SSE3 MMX */ + { MASK_SSE3, CODE_FOR_addsubv4sf3, "__builtin_ia32_addsubps", IX86_BUILTIN_ADDSUBPS, 0, 0 }, + { MASK_SSE3, CODE_FOR_addsubv2df3, "__builtin_ia32_addsubpd", IX86_BUILTIN_ADDSUBPD, 0, 0 }, + { MASK_SSE3, CODE_FOR_haddv4sf3, "__builtin_ia32_haddps", IX86_BUILTIN_HADDPS, 0, 0 }, + { MASK_SSE3, CODE_FOR_haddv2df3, "__builtin_ia32_haddpd", IX86_BUILTIN_HADDPD, 0, 0 }, + { MASK_SSE3, CODE_FOR_hsubv4sf3, "__builtin_ia32_hsubps", IX86_BUILTIN_HSUBPS, 0, 0 }, + { MASK_SSE3, CODE_FOR_hsubv2df3, "__builtin_ia32_hsubpd", IX86_BUILTIN_HSUBPD, 0, 0 } }; static const struct builtin_description bdesc_1arg[] = @@ -13126,10 +13126,10 @@ static const struct builtin_description bdesc_1arg[] = { MASK_SSE2, CODE_FOR_sse2_movq, 0, IX86_BUILTIN_MOVQ, 0, 0 }, - /* PNI */ - { MASK_PNI, CODE_FOR_movshdup, 0, IX86_BUILTIN_MOVSHDUP, 0, 0 }, - { MASK_PNI, CODE_FOR_movsldup, 0, IX86_BUILTIN_MOVSLDUP, 0, 0 }, - { MASK_PNI, CODE_FOR_movddup, 0, IX86_BUILTIN_MOVDDUP, 0, 0 } + /* SSE3 */ + { MASK_SSE3, CODE_FOR_movshdup, 0, IX86_BUILTIN_MOVSHDUP, 0, 0 }, + { MASK_SSE3, CODE_FOR_movsldup, 0, IX86_BUILTIN_MOVSLDUP, 0, 0 }, + { MASK_SSE3, CODE_FOR_movddup, 0, IX86_BUILTIN_MOVDDUP, 0, 0 } }; void @@ -13755,23 +13755,23 @@ ix86_init_mmx_sse_builtins (void) def_builtin (MASK_SSE2, "__builtin_ia32_pmaddwd128", v4si_ftype_v8hi_v8hi, IX86_BUILTIN_PMADDWD128); /* Prescott New Instructions. */ - def_builtin (MASK_PNI, "__builtin_ia32_monitor", + def_builtin (MASK_SSE3, "__builtin_ia32_monitor", void_ftype_pcvoid_unsigned_unsigned, IX86_BUILTIN_MONITOR); - def_builtin (MASK_PNI, "__builtin_ia32_mwait", + def_builtin (MASK_SSE3, "__builtin_ia32_mwait", void_ftype_unsigned_unsigned, IX86_BUILTIN_MWAIT); - def_builtin (MASK_PNI, "__builtin_ia32_movshdup", + def_builtin (MASK_SSE3, "__builtin_ia32_movshdup", v4sf_ftype_v4sf, IX86_BUILTIN_MOVSHDUP); - def_builtin (MASK_PNI, "__builtin_ia32_movsldup", + def_builtin (MASK_SSE3, "__builtin_ia32_movsldup", v4sf_ftype_v4sf, IX86_BUILTIN_MOVSLDUP); - def_builtin (MASK_PNI, "__builtin_ia32_lddqu", + def_builtin (MASK_SSE3, "__builtin_ia32_lddqu", v16qi_ftype_pcchar, IX86_BUILTIN_LDDQU); - def_builtin (MASK_PNI, "__builtin_ia32_loadddup", + def_builtin (MASK_SSE3, "__builtin_ia32_loadddup", v2df_ftype_pcdouble, IX86_BUILTIN_LOADDDUP); - def_builtin (MASK_PNI, "__builtin_ia32_movddup", + def_builtin (MASK_SSE3, "__builtin_ia32_movddup", v2df_ftype_v2df, IX86_BUILTIN_MOVDDUP); } diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h index 5cbddb13978..03e64fff50b 100644 --- a/gcc/config/i386/i386.h +++ b/gcc/config/i386/i386.h @@ -121,7 +121,7 @@ extern int target_flags; #define MASK_MMX 0x00002000 /* Support MMX regs/builtins */ #define MASK_SSE 0x00004000 /* Support SSE regs/builtins */ #define MASK_SSE2 0x00008000 /* Support SSE2 regs/builtins */ -#define MASK_PNI 0x00010000 /* Support PNI regs/builtins */ +#define MASK_SSE3 0x00010000 /* Support SSE3 regs/builtins */ #define MASK_3DNOW 0x00020000 /* Support 3Dnow builtins */ #define MASK_3DNOW_A 0x00040000 /* Support Athlon 3Dnow builtins */ #define MASK_128BIT_LONG_DOUBLE 0x00080000 /* long double size is 128bit */ @@ -304,7 +304,7 @@ extern int x86_prefetch_sse; #define TARGET_SSE ((target_flags & MASK_SSE) != 0) #define TARGET_SSE2 ((target_flags & MASK_SSE2) != 0) -#define TARGET_PNI ((target_flags & MASK_PNI) != 0) +#define TARGET_SSE3 ((target_flags & MASK_SSE3) != 0) #define TARGET_SSE_MATH ((ix86_fpmath & FPMATH_SSE) != 0) #define TARGET_MIX_SSE_I387 ((ix86_fpmath & FPMATH_SSE) \ && (ix86_fpmath & FPMATH_387)) @@ -400,10 +400,10 @@ extern int x86_prefetch_sse; N_("Support MMX, SSE and SSE2 built-in functions and code generation") }, \ { "no-sse2", -MASK_SSE2, \ N_("Do not support MMX, SSE and SSE2 built-in functions and code generation") }, \ - { "pni", MASK_PNI, \ - N_("Support MMX, SSE, SSE2 and PNI built-in functions and code generation") },\ - { "no-pni", -MASK_PNI, \ - N_("Do not support MMX, SSE, SSE2 and PNI built-in functions and code generation") },\ + { "sse3", MASK_SSE3, \ + N_("Support MMX, SSE, SSE2 and SSE3 built-in functions and code generation") },\ + { "no-sse3", -MASK_SSE3, \ + N_("Do not support MMX, SSE, SSE2 and SSE3 built-in functions and code generation") },\ { "128bit-long-double", MASK_128BIT_LONG_DOUBLE, \ N_("sizeof(long double) is 16") }, \ { "96bit-long-double", -MASK_128BIT_LONG_DOUBLE, \ @@ -617,8 +617,8 @@ extern int x86_prefetch_sse; builtin_define ("__SSE__"); \ if (TARGET_SSE2) \ builtin_define ("__SSE2__"); \ - if (TARGET_PNI) \ - builtin_define ("__PNI__"); \ + if (TARGET_SSE3) \ + builtin_define ("__SSE3__"); \ if (TARGET_SSE_MATH && TARGET_SSE) \ builtin_define ("__SSE_MATH__"); \ if (TARGET_SSE_MATH && TARGET_SSE2) \ diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index abd7f3dd773..3ee0ec14b6f 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -22930,13 +22930,13 @@ [(set_attr "type" "sse") (set_attr "memory" "unknown")]) -;; PNI +;; SSE3 (define_insn "mwait" [(unspec_volatile [(match_operand:SI 0 "register_operand" "a") (match_operand:SI 1 "register_operand" "c")] UNSPECV_MWAIT)] - "TARGET_PNI" + "TARGET_SSE3" "mwait\t%0, %1" [(set_attr "length" "3")]) @@ -22945,18 +22945,18 @@ (match_operand:SI 1 "register_operand" "c") (match_operand:SI 2 "register_operand" "d")] UNSPECV_MONITOR)] - "TARGET_PNI" + "TARGET_SSE3" "monitor\t%0, %1, %2" [(set_attr "length" "3")]) -;; PNI arithmetic +;; SSE3 arithmetic (define_insn "addsubv4sf3" [(set (match_operand:V4SF 0 "register_operand" "=x") (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "0") (match_operand:V4SF 2 "nonimmediate_operand" "xm")] UNSPEC_ADDSUB))] - "TARGET_PNI" + "TARGET_SSE3" "addsubps\t{%2, %0|%0, %2}" [(set_attr "type" "sseadd") (set_attr "mode" "V4SF")]) @@ -22966,7 +22966,7 @@ (unspec:V2DF [(match_operand:V2DF 1 "register_operand" "0") (match_operand:V2DF 2 "nonimmediate_operand" "xm")] UNSPEC_ADDSUB))] - "TARGET_PNI" + "TARGET_SSE3" "addsubpd\t{%2, %0|%0, %2}" [(set_attr "type" "sseadd") (set_attr "mode" "V2DF")]) @@ -22976,7 +22976,7 @@ (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "0") (match_operand:V4SF 2 "nonimmediate_operand" "xm")] UNSPEC_HADD))] - "TARGET_PNI" + "TARGET_SSE3" "haddps\t{%2, %0|%0, %2}" [(set_attr "type" "sseadd") (set_attr "mode" "V4SF")]) @@ -22986,7 +22986,7 @@ (unspec:V2DF [(match_operand:V2DF 1 "register_operand" "0") (match_operand:V2DF 2 "nonimmediate_operand" "xm")] UNSPEC_HADD))] - "TARGET_PNI" + "TARGET_SSE3" "haddpd\t{%2, %0|%0, %2}" [(set_attr "type" "sseadd") (set_attr "mode" "V2DF")]) @@ -22996,7 +22996,7 @@ (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "0") (match_operand:V4SF 2 "nonimmediate_operand" "xm")] UNSPEC_HSUB))] - "TARGET_PNI" + "TARGET_SSE3" "hsubps\t{%2, %0|%0, %2}" [(set_attr "type" "sseadd") (set_attr "mode" "V4SF")]) @@ -23006,7 +23006,7 @@ (unspec:V2DF [(match_operand:V2DF 1 "register_operand" "0") (match_operand:V2DF 2 "nonimmediate_operand" "xm")] UNSPEC_HSUB))] - "TARGET_PNI" + "TARGET_SSE3" "hsubpd\t{%2, %0|%0, %2}" [(set_attr "type" "sseadd") (set_attr "mode" "V2DF")]) @@ -23015,7 +23015,7 @@ [(set (match_operand:V4SF 0 "register_operand" "=x") (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm")] UNSPEC_MOVSHDUP))] - "TARGET_PNI" + "TARGET_SSE3" "movshdup\t{%1, %0|%0, %1}" [(set_attr "type" "sse") (set_attr "mode" "V4SF")]) @@ -23024,7 +23024,7 @@ [(set (match_operand:V4SF 0 "register_operand" "=x") (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm")] UNSPEC_MOVSLDUP))] - "TARGET_PNI" + "TARGET_SSE3" "movsldup\t{%1, %0|%0, %1}" [(set_attr "type" "sse") (set_attr "mode" "V4SF")]) @@ -23033,7 +23033,7 @@ [(set (match_operand:V16QI 0 "register_operand" "=x") (unspec:V16QI [(match_operand:V16QI 1 "memory_operand" "m")] UNSPEC_LDQQU))] - "TARGET_PNI" + "TARGET_SSE3" "lddqu\t{%1, %0|%0, %1}" [(set_attr "type" "ssecvt") (set_attr "mode" "TI")]) @@ -23041,7 +23041,7 @@ (define_insn "loadddup" [(set (match_operand:V2DF 0 "register_operand" "=x") (vec_duplicate:V2DF (match_operand:DF 1 "memory_operand" "m")))] - "TARGET_PNI" + "TARGET_SSE3" "movddup\t{%1, %0|%0, %1}" [(set_attr "type" "ssecvt") (set_attr "mode" "DF")]) @@ -23051,7 +23051,7 @@ (vec_duplicate:V2DF (vec_select:DF (match_operand:V2DF 1 "register_operand" "x") (parallel [(const_int 0)]))))] - "TARGET_PNI" + "TARGET_SSE3" "movddup\t{%1, %0|%0, %1}" [(set_attr "type" "ssecvt") (set_attr "mode" "DF")]) diff --git a/gcc/config/i386/pmmintrin.h b/gcc/config/i386/pmmintrin.h index 5b215e8e53c..3b18e2a11bd 100644 --- a/gcc/config/i386/pmmintrin.h +++ b/gcc/config/i386/pmmintrin.h @@ -30,7 +30,7 @@ #ifndef _PMMINTRIN_H_INCLUDED #define _PMMINTRIN_H_INCLUDED -#ifdef __PNI__ +#ifdef __SSE3__ #include #include @@ -127,6 +127,6 @@ _mm_mwait (unsigned int __E, unsigned int __H) #define _mm_mwait(E, H) __builtin_ia32_mwait ((E), (H)) #endif -#endif /* __PNI__ */ +#endif /* __SSE3__ */ #endif /* _PMMINTRIN_H_INCLUDED */ diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index 13bd75f4e13..b396227bb84 100644 --- a/gcc/doc/extend.texi +++ b/gcc/doc/extend.texi @@ -5977,7 +5977,7 @@ Generates the @code{movhps} machine instruction as a store to memory. Generates the @code{movlps} machine instruction as a store to memory. @end table -The following built-in functions are available when @option{-mpni} is used. +The following built-in functions are available when @option{-msse3} is used. All of them generate the machine instruction that is part of the name. @smallexample @@ -5995,7 +5995,7 @@ v4sf __builtin_ia32_movsldup (v4sf) void __builtin_ia32_mwait (unsigned int, unsigned int) @end smallexample -The following built-in functions are available when @option{-mpni} is used. +The following built-in functions are available when @option{-msse3} is used. @table @code @item v2df __builtin_ia32_loadddup (double const *) diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index b703dc39b99..2607e403246 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -488,7 +488,7 @@ in the following sections. -mno-fp-ret-in-387 -msoft-float -msvr3-shlib @gol -mno-wide-multiply -mrtd -malign-double @gol -mpreferred-stack-boundary=@var{num} @gol --mmmx -msse -msse2 -mpni -m3dnow @gol +-mmmx -msse -msse2 -msse3 -m3dnow @gol -mthreads -mno-align-stringops -minline-all-stringops @gol -mpush-args -maccumulate-outgoing-args -m128bit-long-double @gol -m96bit-long-double -mregparm=@var{num} -momit-leaf-frame-pointer @gol @@ -8385,8 +8385,8 @@ preferred alignment to @option{-mpreferred-stack-boundary=2}. @itemx -mno-sse @item -msse2 @itemx -mno-sse2 -@item -mpni -@itemx -mno-pni +@item -msse3 +@itemx -mno-sse3 @item -m3dnow @itemx -mno-3dnow @opindex mmmx @@ -8396,7 +8396,7 @@ preferred alignment to @option{-mpreferred-stack-boundary=2}. @opindex m3dnow @opindex mno-3dnow These switches enable or disable the use of built-in functions that allow -direct access to the MMX, SSE, SSE2, PNI and 3Dnow extensions of the +direct access to the MMX, SSE, SSE2, SSE3 and 3Dnow extensions of the instruction set. @xref{X86 Built-in Functions}, for details of the functions enabled