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arm.c (MAX_INSN_PER_IT_BLOCK): New macro.

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2013-06-05  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	* config/arm/arm.c (MAX_INSN_PER_IT_BLOCK): New macro.
	(arm_option_override): Override arm_restrict_it where appropriate.
	(thumb2_final_prescan_insn): Use MAX_INSN_PER_IT_BLOCK.
	* config/arm/arm.opt (mrestrict-it): New command-line option.
	* doc/invoke.texi: Document -mrestrict-it.

From-SVN: r199694
This commit is contained in:
Kyrylo Tkachov 2013-06-05 12:41:55 +00:00 • committed by Kyrylo Tkachov
parent 05fe45b882
commit 9912dbe5c7
4 changed files with 30 additions and 2 deletions
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8
gcc/ChangeLog
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@ -1,3 +1,11 @@
2013-06-05 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/arm/arm.c (MAX_INSN_PER_IT_BLOCK): New macro.
(arm_option_override): Override arm_restrict_it where appropriate.
(thumb2_final_prescan_insn): Use MAX_INSN_PER_IT_BLOCK.
* config/arm/arm.opt (mrestrict-it): New command-line option.
* doc/invoke.texi: Document -mrestrict-it.
2013-06-05 David Malcolm <dmalcolm@redhat.com>
* tsan.c (tsan_atomic_table): Make const.

11
gcc/config/arm/arm.c
View file

@ -662,6 +662,10 @@ static const struct attribute_spec arm_attribute_table[] =
#undef TARGET_ASAN_SHADOW_OFFSET
#define TARGET_ASAN_SHADOW_OFFSET arm_asan_shadow_offset
#undef MAX_INSN_PER_IT_BLOCK
#define MAX_INSN_PER_IT_BLOCK (arm_restrict_it ? 1 : 4)
struct gcc_target targetm = TARGET_INITIALIZER;
/* Obstack for minipool constant handling. */
@ -1871,6 +1875,11 @@ arm_option_override (void)
arm_arch_thumb_hwdiv = (insn_flags & FL_THUMB_DIV) != 0;
arm_arch_arm_hwdiv = (insn_flags & FL_ARM_DIV) != 0;
arm_tune_cortex_a9 = (arm_tune == cortexa9) != 0;
if (arm_restrict_it == 2)
arm_restrict_it = arm_arch8 && TARGET_THUMB2;
if (!TARGET_THUMB2)
arm_restrict_it = 0;
/* If we are not using the default (ARM mode) section anchor offset
ranges, then set the correct ranges now. */
@ -19593,7 +19602,7 @@ thumb2_final_prescan_insn (rtx insn)
break;
/* Allow up to 4 conditionally executed instructions in a block. */
n = get_attr_ce_count (insn);
if (arm_condexec_masklen + n > 4)
if (arm_condexec_masklen + n > MAX_INSN_PER_IT_BLOCK)
break;
predicate = COND_EXEC_TEST (body);

4
gcc/config/arm/arm.opt
View file

@ -239,6 +239,10 @@ mword-relocations
Target Report Var(target_word_relocations) Init(TARGET_DEFAULT_WORD_RELOCATIONS)
Only generate absolute relocations on word sized values.
mrestrict-it
Target Report Var(arm_restrict_it) Init(2)
Generate IT blocks appropriate for ARMv8.
mfix-cortex-m3-ldrd
Target Report Var(fix_cm3_ldrd) Init(2)
Avoid overlapping destination and address registers on LDRD instructions

9
gcc/doc/invoke.texi
View file

@ -512,7 +512,8 @@ Objective-C and Objective-C++ Dialects}.
-mword-relocations @gol
-mfix-cortex-m3-ldrd @gol
-munaligned-access @gol
-mneon-for-64bits}
-mneon-for-64bits @gol
-mrestrict-it}
@emph{AVR Options}
@gccoptlist{-mmcu=@var{mcu} -maccumulate-args -mbranch-cost=@var{cost} @gol
@ -11633,6 +11634,12 @@ defined.
Enables using Neon to handle scalar 64-bits operations. This is
disabled by default since the cost of moving data from core registers
to Neon is high.
@item -mrestrict-it
@opindex mrestrict-it
Restricts generation of IT blocks to conform to the rules of ARMv8.
IT blocks can only contain a single 16-bit instruction from a select
set of instructions. This option is on by default for ARMv8 Thumb mode.
@end table
@node AVR Options