From 9912dbe5c7d8c715d6506380ef62a3377297f4b4 Mon Sep 17 00:00:00 2001 From: Kyrylo Tkachov Date: Wed, 5 Jun 2013 12:41:55 +0000 Subject: [PATCH] arm.c (MAX_INSN_PER_IT_BLOCK): New macro. 2013-06-05 Kyrylo Tkachov * config/arm/arm.c (MAX_INSN_PER_IT_BLOCK): New macro. (arm_option_override): Override arm_restrict_it where appropriate. (thumb2_final_prescan_insn): Use MAX_INSN_PER_IT_BLOCK. * config/arm/arm.opt (mrestrict-it): New command-line option. * doc/invoke.texi: Document -mrestrict-it. From-SVN: r199694 --- gcc/ChangeLog | 8 ++++++++ gcc/config/arm/arm.c | 11 ++++++++++- gcc/config/arm/arm.opt | 4 ++++ gcc/doc/invoke.texi | 9 ++++++++- 4 files changed, 30 insertions(+), 2 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 0944298057c..391a5292fd1 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,11 @@ +2013-06-05 Kyrylo Tkachov + + * config/arm/arm.c (MAX_INSN_PER_IT_BLOCK): New macro. + (arm_option_override): Override arm_restrict_it where appropriate. + (thumb2_final_prescan_insn): Use MAX_INSN_PER_IT_BLOCK. + * config/arm/arm.opt (mrestrict-it): New command-line option. + * doc/invoke.texi: Document -mrestrict-it. + 2013-06-05 David Malcolm * tsan.c (tsan_atomic_table): Make const. diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 42f52c7082f..63eb2b76089 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -662,6 +662,10 @@ static const struct attribute_spec arm_attribute_table[] = #undef TARGET_ASAN_SHADOW_OFFSET #define TARGET_ASAN_SHADOW_OFFSET arm_asan_shadow_offset +#undef MAX_INSN_PER_IT_BLOCK +#define MAX_INSN_PER_IT_BLOCK (arm_restrict_it ? 1 : 4) + + struct gcc_target targetm = TARGET_INITIALIZER; /* Obstack for minipool constant handling. */ @@ -1871,6 +1875,11 @@ arm_option_override (void) arm_arch_thumb_hwdiv = (insn_flags & FL_THUMB_DIV) != 0; arm_arch_arm_hwdiv = (insn_flags & FL_ARM_DIV) != 0; arm_tune_cortex_a9 = (arm_tune == cortexa9) != 0; + if (arm_restrict_it == 2) + arm_restrict_it = arm_arch8 && TARGET_THUMB2; + + if (!TARGET_THUMB2) + arm_restrict_it = 0; /* If we are not using the default (ARM mode) section anchor offset ranges, then set the correct ranges now. */ @@ -19593,7 +19602,7 @@ thumb2_final_prescan_insn (rtx insn) break; /* Allow up to 4 conditionally executed instructions in a block. */ n = get_attr_ce_count (insn); - if (arm_condexec_masklen + n > 4) + if (arm_condexec_masklen + n > MAX_INSN_PER_IT_BLOCK) break; predicate = COND_EXEC_TEST (body); diff --git a/gcc/config/arm/arm.opt b/gcc/config/arm/arm.opt index afb42421c06..b9ae2b09682 100644 --- a/gcc/config/arm/arm.opt +++ b/gcc/config/arm/arm.opt @@ -239,6 +239,10 @@ mword-relocations Target Report Var(target_word_relocations) Init(TARGET_DEFAULT_WORD_RELOCATIONS) Only generate absolute relocations on word sized values. +mrestrict-it +Target Report Var(arm_restrict_it) Init(2) +Generate IT blocks appropriate for ARMv8. + mfix-cortex-m3-ldrd Target Report Var(fix_cm3_ldrd) Init(2) Avoid overlapping destination and address registers on LDRD instructions diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index de57609540f..b7b32f73b75 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -512,7 +512,8 @@ Objective-C and Objective-C++ Dialects}. -mword-relocations @gol -mfix-cortex-m3-ldrd @gol -munaligned-access @gol --mneon-for-64bits} +-mneon-for-64bits @gol +-mrestrict-it} @emph{AVR Options} @gccoptlist{-mmcu=@var{mcu} -maccumulate-args -mbranch-cost=@var{cost} @gol @@ -11633,6 +11634,12 @@ defined. Enables using Neon to handle scalar 64-bits operations. This is disabled by default since the cost of moving data from core registers to Neon is high. + +@item -mrestrict-it +@opindex mrestrict-it +Restricts generation of IT blocks to conform to the rules of ARMv8. +IT blocks can only contain a single 16-bit instruction from a select +set of instructions. This option is on by default for ARMv8 Thumb mode. @end table @node AVR Options