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libatomic: Handle AVX+CX16 ZHAOXIN like Intel for 16b atomic [PR104688]

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PR target/104688

libatomic/ChangeLog:

	* config/x86/init.c (__libat_feat1_init): Don't clear
	bit_AVX on ZHAOXIN CPUs.
This commit is contained in:
mayshao 2024-07-18 22:43:00 +02:00 • committed by Uros Bizjak
parent 9690fb3a43
commit 9846b0916c
1 changed files with 7 additions and 3 deletions
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10
libatomic/config/x86/init.c
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@ -41,11 +41,15 @@ __libat_feat1_init (void)
{
/* Intel SDM guarantees that 16-byte VMOVDQA on 16-byte aligned
address is atomic, and AMD is going to do something similar soon.
We don't have a guarantee from vendors of other CPUs with AVX,
like Zhaoxin and VIA. */
Zhaoxin also guarantees this. We don't have a guarantee
from vendors of other CPUs with AVX, like VIA. */
unsigned int family = (eax >> 8) & 0x0f;
unsigned int ecx2;
__cpuid (0, eax, ebx, ecx2, edx);
if (ecx2 != signature_INTEL_ecx && ecx2 != signature_AMD_ecx)
if (ecx2 != signature_INTEL_ecx
&& ecx2 != signature_AMD_ecx
&& !(ecx2 == signature_CENTAUR_ecx && family > 6)
&& ecx2 != signature_SHANGHAI_ecx)
FEAT1_REGISTER &= ~bit_AVX;
}
#endif