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[amdgcn] Fix ambiguous .md attribute uses

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This patch is part of a series that fixes ambiguous attribute
uses in .md files, i.e. cases in which attributes didn't use
<ITER:ATTR> to specify an iterator, and in which <ATTR> could
have different values depending on the iterator chosen.

I think this is a genuine bugfix for the case in which the 1REG_MODE
and 1REG_ALT are different, since previously we would use the 1REG_MODE
for both the comparison and the select, even though the operands being
compared are 1REG_ALT rather than 1REG_MODE.

2019-07-06  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	* config/gcn/gcn-valu.md
	(vcond<VEC_1REG_MODE:mode><VEC_1REG_ALT:mode>): Use
	gen_vec_cmp<VEC_1REG_ALT:mode>di rather than (implicitly)
	gen_vec_cmp<VEC_1REG_MODE:mode>di.  Explicitly use
	gen_vcond_mask_<VEC_1REG_MODE:mode>di.
	(vcond<VEC_1REG_MODE:mode><VEC_1REG_ALT:mode>_exec): Likewise,
	but using the _exec comparison patterns.
	(vcondu<VEC_1REG_INT_MODE:mode><VEC_1REG_INT_ALT:mode>): Use
	gen_vec_cmp<VEC_1REG_INT_ALT:mode>di rather than (implicitly)
	gen_vec_cmp<VEC_1REG_INT_MODE:mode>di.  Explicitly use
	gen_vcond_mask_<VEC_1REG_INT_MODE:mode>di.
	(vcondu<VEC_1REG_INT_MODE:mode><VEC_1REG_INT_ALT:mode>_exec): Likewise,
	but using the _exec comparison patterns.

From-SVN: r273159
This commit is contained in:
Richard Sandiford 2019-07-06 08:26:02 +00:00 • committed by Richard Sandiford
parent 193bee751a
commit 96eb1765a3
2 changed files with 32 additions and 16 deletions
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16
gcc/ChangeLog
View file

@ -1,3 +1,19 @@
2019-07-06 Richard Sandiford <richard.sandiford@arm.com>
* config/gcn/gcn-valu.md
(vcond<VEC_1REG_MODE:mode><VEC_1REG_ALT:mode>): Use
gen_vec_cmp<VEC_1REG_ALT:mode>di rather than (implicitly)
gen_vec_cmp<VEC_1REG_MODE:mode>di. Explicitly use
gen_vcond_mask_<VEC_1REG_MODE:mode>di.
(vcond<VEC_1REG_MODE:mode><VEC_1REG_ALT:mode>_exec): Likewise,
but using the _exec comparison patterns.
(vcondu<VEC_1REG_INT_MODE:mode><VEC_1REG_INT_ALT:mode>): Use
gen_vec_cmp<VEC_1REG_INT_ALT:mode>di rather than (implicitly)
gen_vec_cmp<VEC_1REG_INT_MODE:mode>di. Explicitly use
gen_vcond_mask_<VEC_1REG_INT_MODE:mode>di.
(vcondu<VEC_1REG_INT_MODE:mode><VEC_1REG_INT_ALT:mode>_exec): Likewise,
but using the _exec comparison patterns.
2019-07-06 Richard Sandiford <richard.sandiford@arm.com>
* config/arm/sync.md

32
gcc/config/gcn/gcn-valu.md
View file

@ -2574,10 +2574,10 @@
""
{
rtx tmp = gen_reg_rtx (DImode);
emit_insn (gen_vec_cmp<mode>di (tmp, operands[3], operands[4],
operands[5]));
emit_insn (gen_vcond_mask_<mode>di (operands[0], operands[1], operands[2],
tmp));
emit_insn (gen_vec_cmp<VEC_1REG_ALT:mode>di
(tmp, operands[3], operands[4], operands[5]));
emit_insn (gen_vcond_mask_<VEC_1REG_MODE:mode>di
(operands[0], operands[1], operands[2], tmp));
DONE;
})
@ -2592,10 +2592,10 @@
""
{
rtx tmp = gen_reg_rtx (DImode);
emit_insn (gen_vec_cmp<mode>di_exec (tmp, operands[3], operands[4],
operands[5], operands[6]));
emit_insn (gen_vcond_mask_<mode>di (operands[0], operands[1], operands[2],
tmp));
emit_insn (gen_vec_cmp<VEC_1REG_ALT:mode>di_exec
(tmp, operands[3], operands[4], operands[5], operands[6]));
emit_insn (gen_vcond_mask_<VEC_1REG_MODE:mode>di
(operands[0], operands[1], operands[2], tmp));
DONE;
})
@ -2609,10 +2609,10 @@
""
{
rtx tmp = gen_reg_rtx (DImode);
emit_insn (gen_vec_cmp<mode>di (tmp, operands[3], operands[4],
operands[5]));
emit_insn (gen_vcond_mask_<mode>di (operands[0], operands[1], operands[2],
tmp));
emit_insn (gen_vec_cmp<VEC_1REG_INT_ALT:mode>di
(tmp, operands[3], operands[4], operands[5]));
emit_insn (gen_vcond_mask_<VEC_1REG_INT_MODE:mode>di
(operands[0], operands[1], operands[2], tmp));
DONE;
})
@ -2627,10 +2627,10 @@
""
{
rtx tmp = gen_reg_rtx (DImode);
emit_insn (gen_vec_cmp<mode>di_exec (tmp, operands[3], operands[4],
operands[5], operands[6]));
emit_insn (gen_vcond_mask_<mode>di (operands[0], operands[1], operands[2],
tmp));
emit_insn (gen_vec_cmp<VEC_1REG_INT_ALT:mode>di_exec
(tmp, operands[3], operands[4], operands[5], operands[6]));
emit_insn (gen_vcond_mask_<VEC_1REG_INT_MODE:mode>di
(operands[0], operands[1], operands[2], tmp));
DONE;
})