diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 1ae6b1c6a46..9dc0e093690 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,19 @@
+2019-07-06  Richard Sandiford  <richard.sandiford@arm.com>
+
+	* config/gcn/gcn-valu.md
+	(vcond<VEC_1REG_MODE:mode><VEC_1REG_ALT:mode>): Use
+	gen_vec_cmp<VEC_1REG_ALT:mode>di rather than (implicitly)
+	gen_vec_cmp<VEC_1REG_MODE:mode>di.  Explicitly use
+	gen_vcond_mask_<VEC_1REG_MODE:mode>di.
+	(vcond<VEC_1REG_MODE:mode><VEC_1REG_ALT:mode>_exec): Likewise,
+	but using the _exec comparison patterns.
+	(vcondu<VEC_1REG_INT_MODE:mode><VEC_1REG_INT_ALT:mode>): Use
+	gen_vec_cmp<VEC_1REG_INT_ALT:mode>di rather than (implicitly)
+	gen_vec_cmp<VEC_1REG_INT_MODE:mode>di.  Explicitly use
+	gen_vcond_mask_<VEC_1REG_INT_MODE:mode>di.
+	(vcondu<VEC_1REG_INT_MODE:mode><VEC_1REG_INT_ALT:mode>_exec): Likewise,
+	but using the _exec comparison patterns.
+
 2019-07-06  Richard Sandiford  <richard.sandiford@arm.com>
 
 	* config/arm/sync.md
diff --git a/gcc/config/gcn/gcn-valu.md b/gcc/config/gcn/gcn-valu.md
index 3cc59dd1cd6..c7e8b160943 100644
--- a/gcc/config/gcn/gcn-valu.md
+++ b/gcc/config/gcn/gcn-valu.md
@@ -2574,10 +2574,10 @@
   ""
   {
     rtx tmp = gen_reg_rtx (DImode);
-    emit_insn (gen_vec_cmp<mode>di (tmp, operands[3], operands[4],
-				    operands[5]));
-    emit_insn (gen_vcond_mask_<mode>di (operands[0], operands[1], operands[2],
-					tmp));
+    emit_insn (gen_vec_cmp<VEC_1REG_ALT:mode>di
+	       (tmp, operands[3], operands[4], operands[5]));
+    emit_insn (gen_vcond_mask_<VEC_1REG_MODE:mode>di
+	       (operands[0], operands[1], operands[2], tmp));
     DONE;
   })
 
@@ -2592,10 +2592,10 @@
   ""
   {
     rtx tmp = gen_reg_rtx (DImode);
-    emit_insn (gen_vec_cmp<mode>di_exec (tmp, operands[3], operands[4],
-					 operands[5], operands[6]));
-    emit_insn (gen_vcond_mask_<mode>di (operands[0], operands[1], operands[2],
-					tmp));
+    emit_insn (gen_vec_cmp<VEC_1REG_ALT:mode>di_exec
+	       (tmp, operands[3], operands[4], operands[5], operands[6]));
+    emit_insn (gen_vcond_mask_<VEC_1REG_MODE:mode>di
+	       (operands[0], operands[1], operands[2], tmp));
     DONE;
   })
 
@@ -2609,10 +2609,10 @@
   ""
   {
     rtx tmp = gen_reg_rtx (DImode);
-    emit_insn (gen_vec_cmp<mode>di (tmp, operands[3], operands[4],
-				    operands[5]));
-    emit_insn (gen_vcond_mask_<mode>di (operands[0], operands[1], operands[2],
-				        tmp));
+    emit_insn (gen_vec_cmp<VEC_1REG_INT_ALT:mode>di
+	       (tmp, operands[3], operands[4], operands[5]));
+    emit_insn (gen_vcond_mask_<VEC_1REG_INT_MODE:mode>di
+	       (operands[0], operands[1], operands[2], tmp));
     DONE;
   })
 
@@ -2627,10 +2627,10 @@
   ""
   {
     rtx tmp = gen_reg_rtx (DImode);
-    emit_insn (gen_vec_cmp<mode>di_exec (tmp, operands[3], operands[4],
-					 operands[5], operands[6]));
-    emit_insn (gen_vcond_mask_<mode>di (operands[0], operands[1], operands[2],
-				        tmp));
+    emit_insn (gen_vec_cmp<VEC_1REG_INT_ALT:mode>di_exec
+	       (tmp, operands[3], operands[4], operands[5], operands[6]));
+    emit_insn (gen_vcond_mask_<VEC_1REG_INT_MODE:mode>di
+	       (operands[0], operands[1], operands[2], tmp));
     DONE;
   })