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RISC-V: Split off shift patterns for autovectorization.

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This patch splits off the shift patterns of the binop patterns.
This is necessary as the scalar shifts require a Pmode operand
as shift count.  To this end, a new iterator any_int_binop_no_shift
is introduced.  At a later point when the binops are split up
further in commutative and non-commutative patterns (which both
do not include the shift patterns) we might not need this anymore.

gcc/ChangeLog:

	* config/riscv/autovec.md (<optab><mode>3): Add scalar shift
	pattern.
	(v<optab><mode>3): Add vector shift pattern.
	* config/riscv/vector-iterators.md: New iterator.
This commit is contained in:
Robin Dapp 2023-05-10 09:52:43 +02:00
parent 84d2899638
commit 8c08201f06
2 changed files with 50 additions and 1 deletions
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47
gcc/config/riscv/autovec.md
View file

@ -97,7 +97,7 @@
(define_expand "<optab><mode>3"
[(set (match_operand:VI 0 "register_operand")
(any_int_binop:VI
(any_int_binop_no_shift:VI
(match_operand:VI 1 "<binop_rhs1_predicate>")
(match_operand:VI 2 "<binop_rhs2_predicate>")))]
"TARGET_VECTOR"
@ -119,3 +119,48 @@
NULL, <VM>mode);
DONE;
})
;; -------------------------------------------------------------------------
;; ---- [INT] Binary shifts by scalar.
;; -------------------------------------------------------------------------
;; Includes:
;; - vsll.vx/vsra.vx/vsrl.vx
;; - vsll.vi/vsra.vi/vsrl.vi
;; -------------------------------------------------------------------------
(define_expand "<optab><mode>3"
[(set (match_operand:VI 0 "register_operand")
(any_shift:VI
(match_operand:VI 1 "register_operand")
(match_operand:<VEL> 2 "csr_operand")))]
"TARGET_VECTOR"
{
if (!CONST_SCALAR_INT_P (operands[2]))
operands[2] = gen_lowpart (Pmode, operands[2]);
riscv_vector::emit_len_binop (code_for_pred_scalar
(<CODE>, <MODE>mode),
operands[0], operands[1], operands[2],
NULL_RTX, <VM>mode, Pmode);
DONE;
})
;; -------------------------------------------------------------------------
;; ---- [INT] Binary shifts by scalar.
;; -------------------------------------------------------------------------
;; Includes:
;; - vsll.vv/vsra.vv/vsrl.vv
;; -------------------------------------------------------------------------
(define_expand "v<optab><mode>3"
[(set (match_operand:VI 0 "register_operand")
(any_shift:VI
(match_operand:VI 1 "register_operand")
(match_operand:VI 2 "vector_shift_operand")))]
"TARGET_VECTOR"
{
riscv_vector::emit_len_binop (code_for_pred
(<CODE>, <MODE>mode),
operands[0], operands[1], operands[2],
NULL_RTX, <VM>mode);
DONE;
})

4
gcc/config/riscv/vector-iterators.md
View file

@ -1409,6 +1409,10 @@
(define_code_iterator any_non_commutative_binop [minus div udiv mod umod])
(define_code_iterator any_int_binop_no_shift
[plus minus and ior xor smax umax smin umin mult div udiv mod umod
])
(define_code_iterator any_sat_int_binop [ss_plus ss_minus us_plus us_minus])
(define_code_iterator sat_int_plus_binop [ss_plus us_plus])
(define_code_iterator sat_int_minus_binop [ss_minus us_minus])