RISC-V: Clarify vlmax and length handling.
This patch tries to improve the wrappers that emit either vlmax or non-vlmax operations. Now, emit_len_op can be used to emit a regular operation. Depending on whether a length != NULL is passed either no VLMAX flags are set or we emit a vsetvli and set VLMAX flags. The patch also adds some comments that describes some of the rationale of the current handling of vlmax/nonvlmax operations. gcc/ChangeLog: * config/riscv/autovec.md: Use renamed functions. * config/riscv/riscv-protos.h (emit_vlmax_op): Rename. (emit_vlmax_reg_op): To this. (emit_nonvlmax_op): Rename. (emit_len_op): To this. (emit_nonvlmax_binop): Rename. (emit_len_binop): To this. * config/riscv/riscv-v.cc (emit_pred_op): Add default parameter. (emit_pred_binop): Remove vlmax_p. (emit_vlmax_op): Rename. (emit_vlmax_reg_op): To this. (emit_nonvlmax_op): Rename. (emit_len_op): To this. (emit_nonvlmax_binop): Rename. (emit_len_binop): To this. (sew64_scalar_helper): Use renamed functions. (expand_tuple_move): Use renamed functions. * config/riscv/riscv.cc (vector_zero_call_used_regs): Use renamed functions. * config/riscv/vector.md: Use renamed functions.
This commit is contained in:
Robin Dapp
parent
b75c9e1037
commit
84d2899638
5 changed files with 91 additions and 69 deletions
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@ -31,8 +31,8 @@
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(match_operand 3 "const_0_operand")]
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"TARGET_VECTOR"
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{
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riscv_vector::emit_nonvlmax_op (code_for_pred_mov (<MODE>mode), operands[0],
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operands[1], operands[2], <VM>mode);
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riscv_vector::emit_len_op (code_for_pred_mov (<MODE>mode), operands[0],
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operands[1], operands[2], <VM>mode);
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DONE;
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})
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@ -43,8 +43,8 @@
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(match_operand 3 "const_0_operand")]
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"TARGET_VECTOR"
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{
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riscv_vector::emit_nonvlmax_op (code_for_pred_mov (<MODE>mode), operands[0],
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operands[1], operands[2], <VM>mode);
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riscv_vector::emit_len_op (code_for_pred_mov (<MODE>mode), operands[0],
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operands[1], operands[2], <VM>mode);
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DONE;
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})
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@ -106,16 +106,16 @@
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{
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rtx cst;
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gcc_assert (const_vec_duplicate_p(operands[2], &cst));
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riscv_vector::emit_nonvlmax_binop (code_for_pred_scalar
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(<CODE>, <MODE>mode),
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operands[0], operands[1], cst,
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NULL, <VM>mode,
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<VEL>mode);
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riscv_vector::emit_len_binop (code_for_pred_scalar
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(<CODE>, <MODE>mode),
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operands[0], operands[1], cst,
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NULL, <VM>mode,
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<VEL>mode);
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}
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else
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riscv_vector::emit_nonvlmax_binop (code_for_pred
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(<CODE>, <MODE>mode),
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operands[0], operands[1], operands[2],
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NULL, <VM>mode);
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riscv_vector::emit_len_binop (code_for_pred
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(<CODE>, <MODE>mode),
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operands[0], operands[1], operands[2],
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NULL, <VM>mode);
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DONE;
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})
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@ -167,10 +167,10 @@ bool legitimize_move (rtx, rtx, machine_mode);
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void emit_vlmax_vsetvl (machine_mode, rtx);
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void emit_hard_vlmax_vsetvl (machine_mode, rtx);
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void emit_vlmax_op (unsigned, rtx, rtx, machine_mode);
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void emit_vlmax_op (unsigned, rtx, rtx, rtx, machine_mode);
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void emit_nonvlmax_op (unsigned, rtx, rtx, rtx, machine_mode);
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void emit_nonvlmax_binop (unsigned, rtx, rtx, rtx, rtx, machine_mode,
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machine_mode = VOIDmode);
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void emit_vlmax_reg_op (unsigned, rtx, rtx, rtx, machine_mode);
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void emit_len_op (unsigned, rtx, rtx, rtx, machine_mode);
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void emit_len_binop (unsigned, rtx, rtx, rtx, rtx, machine_mode,
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machine_mode = VOIDmode);
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enum vlmul_type get_vlmul (machine_mode);
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unsigned int get_ratio (machine_mode);
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unsigned int get_nf (machine_mode);
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@ -99,27 +99,24 @@ public:
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add_vundef_operand (dest_mode);
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}
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void set_len_and_policy (rtx len, bool vlmax_p)
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void set_len_and_policy (rtx len, bool force_vlmax = false)
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{
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bool vlmax_p = force_vlmax;
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gcc_assert (has_dest);
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gcc_assert (len || vlmax_p);
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if (len)
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add_input_operand (len, Pmode);
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else
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if (!len)
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{
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rtx vlmax = gen_reg_rtx (Pmode);
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emit_vlmax_vsetvl (dest_mode, vlmax);
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add_input_operand (vlmax, Pmode);
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vlmax_p = true;
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len = gen_reg_rtx (Pmode);
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emit_vlmax_vsetvl (dest_mode, len);
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}
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add_input_operand (len, Pmode);
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if (GET_MODE_CLASS (dest_mode) != MODE_VECTOR_BOOL)
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add_policy_operand (get_prefer_tail_policy (), get_prefer_mask_policy ());
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if (vlmax_p)
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add_avl_type_operand (avl_type::VLMAX);
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else
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add_avl_type_operand (avl_type::NONVLMAX);
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add_avl_type_operand (vlmax_p ? avl_type::VLMAX : avl_type::NONVLMAX);
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}
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void expand (enum insn_code icode, bool temporary_volatile_p = false)
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@ -232,14 +229,14 @@ autovec_use_vlmax_p (void)
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/* Emit an RVV unmask && vl mov from SRC to DEST. */
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static void
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emit_pred_op (unsigned icode, rtx mask, rtx dest, rtx src, rtx len,
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machine_mode mask_mode, bool vlmax_p)
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machine_mode mask_mode, bool force_vlmax = false)
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{
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insn_expander<8> e;
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e.set_dest_and_mask (mask, dest, mask_mode);
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e.add_input_operand (src, GET_MODE (src));
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e.set_len_and_policy (len, vlmax_p);
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e.set_len_and_policy (len, force_vlmax);
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e.expand ((enum insn_code) icode, MEM_P (dest) || MEM_P (src));
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}
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@ -248,8 +245,8 @@ emit_pred_op (unsigned icode, rtx mask, rtx dest, rtx src, rtx len,
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specified using SCALAR_MODE. */
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static void
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emit_pred_binop (unsigned icode, rtx mask, rtx dest, rtx src1, rtx src2,
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rtx len, machine_mode mask_mode, machine_mode scalar_mode,
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bool vlmax_p)
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rtx len, machine_mode mask_mode,
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machine_mode scalar_mode = VOIDmode)
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{
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insn_expander<9> e;
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e.set_dest_and_mask (mask, dest, mask_mode);
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@ -267,37 +264,60 @@ emit_pred_binop (unsigned icode, rtx mask, rtx dest, rtx src1, rtx src2,
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else
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e.add_input_operand (src2, scalar_mode);
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e.set_len_and_policy (len, vlmax_p);
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e.set_len_and_policy (len);
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e.expand ((enum insn_code) icode, MEM_P (dest) || MEM_P (src1) || MEM_P (src2));
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}
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/* The RISC-V vsetvli pass uses "known vlmax" operations for optimization.
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Whether or not an instruction actually is a vlmax operation is not
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recognizable from the length operand alone but the avl_type operand
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is used instead. In general, there are two cases:
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- Emit a vlmax operation by passing a NULL length. Here we emit
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a vsetvli with vlmax configuration and set the avl_type to VLMAX.
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- Emit an operation that uses the existing (last-set) length and
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set the avl_type to NONVLMAX.
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Sometimes we also need to set the VLMAX avl_type to an operation that
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already uses a given length register. This can happen during or after
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register allocation when we are not allowed to create a new register.
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For that case we also allow to set the avl_type to VLMAX.
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*/
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/* This function emits a VLMAX vsetvli followed by the actual operation. */
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void
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emit_vlmax_op (unsigned icode, rtx dest, rtx src, machine_mode mask_mode)
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{
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emit_pred_op (icode, NULL_RTX, dest, src, NULL_RTX, mask_mode, true);
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emit_pred_op (icode, NULL_RTX, dest, src, NULL_RTX, mask_mode);
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}
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/* This function emits an operation with a given LEN that is determined
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by a previously emitted VLMAX vsetvli. */
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void
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emit_len_op (unsigned icode, rtx dest, rtx src, rtx len,
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machine_mode mask_mode)
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{
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emit_pred_op (icode, NULL_RTX, dest, src, len, mask_mode);
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}
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/* This function emits an operation with a given LEN that is known to be
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a preceding VLMAX. It also sets the VLMAX flag which allows further
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optimization in the vsetvli pass. */
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void
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emit_vlmax_reg_op (unsigned icode, rtx dest, rtx src, rtx len,
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machine_mode mask_mode)
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{
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emit_pred_op (icode, NULL_RTX, dest, src, len, mask_mode,
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/* Force VLMAX */ true);
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}
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void
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emit_vlmax_op (unsigned icode, rtx dest, rtx src, rtx len,
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machine_mode mask_mode)
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emit_len_binop (unsigned icode, rtx dest, rtx src1, rtx src2, rtx len,
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machine_mode mask_mode, machine_mode scalar_mode)
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{
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emit_pred_op (icode, NULL_RTX, dest, src, len, mask_mode, true);
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}
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void
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emit_nonvlmax_op (unsigned icode, rtx dest, rtx src, rtx len,
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machine_mode mask_mode)
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{
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emit_pred_op (icode, NULL_RTX, dest, src, len, mask_mode, false);
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}
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void
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emit_nonvlmax_binop (unsigned icode, rtx dest, rtx src1, rtx src2, rtx len,
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machine_mode mask_mode, machine_mode scalar_mode)
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{
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emit_pred_binop (icode, NULL_RTX, dest, src1, src2, len, mask_mode,
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scalar_mode, len ? false : true);
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emit_pred_binop (icode, NULL_RTX, dest, src1, src2, len,
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mask_mode, scalar_mode);
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}
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/* Emit vid.v instruction. */
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@ -345,14 +365,14 @@ expand_vec_series (rtx dest, rtx base, rtx step)
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int shift = exact_log2 (INTVAL (step));
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rtx shift_amount = gen_int_mode (shift, Pmode);
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insn_code icode = code_for_pred_scalar (ASHIFT, mode);
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emit_nonvlmax_binop (icode, step_adj, vid, shift_amount,
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NULL, mask_mode, Pmode);
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emit_len_binop (icode, step_adj, vid, shift_amount,
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NULL, mask_mode, Pmode);
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}
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else
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{
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insn_code icode = code_for_pred_scalar (MULT, mode);
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emit_nonvlmax_binop (icode, step_adj, vid, step,
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NULL, mask_mode, inner_mode);
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emit_len_binop (icode, step_adj, vid, step,
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NULL, mask_mode, inner_mode);
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}
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}
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@ -367,7 +387,7 @@ expand_vec_series (rtx dest, rtx base, rtx step)
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{
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rtx result = gen_reg_rtx (mode);
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insn_code icode = code_for_pred_scalar (PLUS, mode);
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emit_nonvlmax_binop (icode, result, step_adj, base,
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emit_len_binop (icode, result, step_adj, base,
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NULL, mask_mode, inner_mode);
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emit_move_insn (dest, result);
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}
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@ -739,8 +759,8 @@ sew64_scalar_helper (rtx *operands, rtx *scalar_op, rtx vl,
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*scalar_op = force_reg (scalar_mode, *scalar_op);
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rtx tmp = gen_reg_rtx (vector_mode);
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riscv_vector::emit_nonvlmax_op (code_for_pred_broadcast (vector_mode), tmp,
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*scalar_op, vl, mask_mode);
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riscv_vector::emit_len_op (code_for_pred_broadcast (vector_mode), tmp,
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*scalar_op, vl, mask_mode);
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emit_vector_func (operands, tmp);
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return true;
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@ -1046,7 +1066,7 @@ expand_tuple_move (machine_mode mask_mode, rtx *ops)
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rtx mem = gen_rtx_MEM (subpart_mode, ops[3]);
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if (fractional_p)
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emit_vlmax_op (code_for_pred_mov (subpart_mode), subreg, mem,
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emit_vlmax_reg_op (code_for_pred_mov (subpart_mode), subreg, mem,
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ops[4], mask_mode);
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else
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emit_move_insn (subreg, mem);
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@ -1068,7 +1088,7 @@ expand_tuple_move (machine_mode mask_mode, rtx *ops)
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rtx mem = gen_rtx_MEM (subpart_mode, ops[3]);
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if (fractional_p)
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emit_vlmax_op (code_for_pred_mov (subpart_mode), mem, subreg,
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emit_vlmax_reg_op (code_for_pred_mov (subpart_mode), mem, subreg,
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ops[4], mask_mode);
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else
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emit_move_insn (mem, subreg);
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@ -7383,8 +7383,8 @@ vector_zero_call_used_regs (HARD_REG_SET need_zeroed_hardregs)
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emitted_vlmax_vsetvl = true;
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}
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riscv_vector::emit_vlmax_op (code_for_pred_mov (mode), target,
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CONST0_RTX (mode), vl, mask_mode);
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riscv_vector::emit_vlmax_reg_op (code_for_pred_mov (mode), target,
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CONST0_RTX (mode), vl, mask_mode);
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SET_HARD_REG_BIT (zeroed_hardregs, regno);
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}
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@ -721,8 +721,9 @@
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else
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{
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riscv_vector::emit_vlmax_vsetvl (<V_FRACT:MODE>mode, operands[2]);
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riscv_vector::emit_vlmax_op (code_for_pred_mov (<V_FRACT:MODE>mode),
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operands[0], operands[1], operands[2], <VM>mode);
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riscv_vector::emit_vlmax_reg_op (code_for_pred_mov (<V_FRACT:MODE>mode),
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operands[0], operands[1], operands[2],
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<VM>mode);
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}
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DONE;
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})
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@ -741,8 +742,9 @@
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else
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{
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riscv_vector::emit_vlmax_vsetvl (<VB:MODE>mode, operands[2]);
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riscv_vector::emit_vlmax_op (code_for_pred_mov (<VB:MODE>mode),
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operands[0], operands[1], operands[2], <VB:MODE>mode);
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riscv_vector::emit_vlmax_reg_op (code_for_pred_mov (<VB:MODE>mode),
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operands[0], operands[1], operands[2],
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<VB:MODE>mode);
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}
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DONE;
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})
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@ -806,7 +808,7 @@
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"TARGET_VECTOR"
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{
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riscv_vector::emit_vlmax_op (code_for_pred_broadcast (<MODE>mode),
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operands[0], operands[1], <VM>mode);
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operands[0], operands[1], <VM>mode);
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DONE;
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}
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)
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