RISC-V: Add vectorized binops and insn_expander helpers.
This patch adds basic binary integer operations support. It is based on Michael Collison's work and makes use of the existing helpers in riscv-c.cc. It introduces emit_nonvlmax_binop which, in turn, uses emit_pred_binop. Setting the destination as well as the mask and the length are factored out into separate functions. gcc/ChangeLog: * config/riscv/autovec.md (<optab><mode>3): Add integer binops. * config/riscv/riscv-protos.h (emit_nonvlmax_binop): Declare. * config/riscv/riscv-v.cc (emit_pred_op): New function. (set_expander_dest_and_mask): New function. (emit_pred_binop): New function. (emit_nonvlmax_binop): New function. Co-authored-by: Michael Collison <collison@rivosinc.com>
This commit is contained in:
Robin Dapp
parent
af595613ac
commit
b75c9e1037
3 changed files with 127 additions and 68 deletions
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@ -82,3 +82,40 @@
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DONE;
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}
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)
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;; ========================================================================
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;; == Vector operations
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;; =========================================================================
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;; -------------------------------------------------------------------------
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;; ---- [INT] Binary operations
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;; -------------------------------------------------------------------------
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;; Includes:
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;; - vadd.vv/vsub.vv/...
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;; - vadd.vi/vsub.vi/...
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;; -------------------------------------------------------------------------
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(define_expand "<optab><mode>3"
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[(set (match_operand:VI 0 "register_operand")
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(any_int_binop:VI
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(match_operand:VI 1 "<binop_rhs1_predicate>")
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(match_operand:VI 2 "<binop_rhs2_predicate>")))]
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"TARGET_VECTOR"
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{
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if (!register_operand (operands[2], <MODE>mode))
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{
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rtx cst;
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gcc_assert (const_vec_duplicate_p(operands[2], &cst));
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riscv_vector::emit_nonvlmax_binop (code_for_pred_scalar
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(<CODE>, <MODE>mode),
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operands[0], operands[1], cst,
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NULL, <VM>mode,
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<VEL>mode);
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}
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else
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riscv_vector::emit_nonvlmax_binop (code_for_pred
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(<CODE>, <MODE>mode),
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operands[0], operands[1], operands[2],
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NULL, <VM>mode);
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DONE;
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})
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@ -169,6 +169,8 @@ void emit_hard_vlmax_vsetvl (machine_mode, rtx);
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void emit_vlmax_op (unsigned, rtx, rtx, machine_mode);
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void emit_vlmax_op (unsigned, rtx, rtx, rtx, machine_mode);
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void emit_nonvlmax_op (unsigned, rtx, rtx, rtx, machine_mode);
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void emit_nonvlmax_binop (unsigned, rtx, rtx, rtx, rtx, machine_mode,
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machine_mode = VOIDmode);
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enum vlmul_type get_vlmul (machine_mode);
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unsigned int get_ratio (machine_mode);
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unsigned int get_nf (machine_mode);
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@ -53,7 +53,7 @@ namespace riscv_vector {
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template <int MAX_OPERANDS> class insn_expander
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{
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public:
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insn_expander () : m_opno (0) {}
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insn_expander () : m_opno (0), has_dest(false) {}
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void add_output_operand (rtx x, machine_mode mode)
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{
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create_output_operand (&m_ops[m_opno++], x, mode);
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@ -84,6 +84,44 @@ public:
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add_input_operand (gen_int_mode (type, Pmode), Pmode);
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}
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void set_dest_and_mask (rtx mask, rtx dest, machine_mode mask_mode)
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{
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dest_mode = GET_MODE (dest);
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has_dest = true;
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add_output_operand (dest, dest_mode);
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if (mask)
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add_input_operand (mask, GET_MODE (mask));
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else
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add_all_one_mask_operand (mask_mode);
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add_vundef_operand (dest_mode);
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}
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void set_len_and_policy (rtx len, bool vlmax_p)
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{
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gcc_assert (has_dest);
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gcc_assert (len || vlmax_p);
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if (len)
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add_input_operand (len, Pmode);
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else
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{
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rtx vlmax = gen_reg_rtx (Pmode);
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emit_vlmax_vsetvl (dest_mode, vlmax);
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add_input_operand (vlmax, Pmode);
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}
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if (GET_MODE_CLASS (dest_mode) != MODE_VECTOR_BOOL)
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add_policy_operand (get_prefer_tail_policy (), get_prefer_mask_policy ());
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if (vlmax_p)
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add_avl_type_operand (avl_type::VLMAX);
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else
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add_avl_type_operand (avl_type::NONVLMAX);
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}
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void expand (enum insn_code icode, bool temporary_volatile_p = false)
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{
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if (temporary_volatile_p)
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@ -97,6 +135,8 @@ public:
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private:
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int m_opno;
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bool has_dest;
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machine_mode dest_mode;
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expand_operand m_ops[MAX_OPERANDS];
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};
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@ -195,39 +235,43 @@ emit_pred_op (unsigned icode, rtx mask, rtx dest, rtx src, rtx len,
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machine_mode mask_mode, bool vlmax_p)
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{
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insn_expander<8> e;
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machine_mode mode = GET_MODE (dest);
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e.add_output_operand (dest, mode);
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if (mask)
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e.add_input_operand (mask, GET_MODE (mask));
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else
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e.add_all_one_mask_operand (mask_mode);
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e.add_vundef_operand (mode);
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e.set_dest_and_mask (mask, dest, mask_mode);
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e.add_input_operand (src, GET_MODE (src));
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if (len)
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e.add_input_operand (len, Pmode);
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else
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{
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rtx vlmax = gen_reg_rtx (Pmode);
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emit_vlmax_vsetvl (mode, vlmax);
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e.add_input_operand (vlmax, Pmode);
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}
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if (GET_MODE_CLASS (mode) != MODE_VECTOR_BOOL)
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e.add_policy_operand (get_prefer_tail_policy (), get_prefer_mask_policy ());
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if (vlmax_p)
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e.add_avl_type_operand (avl_type::VLMAX);
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else
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e.add_avl_type_operand (avl_type::NONVLMAX);
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e.set_len_and_policy (len, vlmax_p);
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e.expand ((enum insn_code) icode, MEM_P (dest) || MEM_P (src));
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}
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/* Emit an RVV binop. If one of SRC1 and SRC2 is a scalar operand, its mode is
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specified using SCALAR_MODE. */
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static void
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emit_pred_binop (unsigned icode, rtx mask, rtx dest, rtx src1, rtx src2,
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rtx len, machine_mode mask_mode, machine_mode scalar_mode,
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bool vlmax_p)
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{
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insn_expander<9> e;
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e.set_dest_and_mask (mask, dest, mask_mode);
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gcc_assert (VECTOR_MODE_P (GET_MODE (src1))
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|| VECTOR_MODE_P (GET_MODE (src2)));
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if (VECTOR_MODE_P (GET_MODE (src1)))
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e.add_input_operand (src1, GET_MODE (src1));
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else
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e.add_input_operand (src1, scalar_mode);
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if (VECTOR_MODE_P (GET_MODE (src2)))
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e.add_input_operand (src2, GET_MODE (src2));
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else
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e.add_input_operand (src2, scalar_mode);
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e.set_len_and_policy (len, vlmax_p);
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e.expand ((enum insn_code) icode, MEM_P (dest) || MEM_P (src1) || MEM_P (src2));
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}
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void
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emit_vlmax_op (unsigned icode, rtx dest, rtx src, machine_mode mask_mode)
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{
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@ -248,49 +292,25 @@ emit_nonvlmax_op (unsigned icode, rtx dest, rtx src, rtx len,
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emit_pred_op (icode, NULL_RTX, dest, src, len, mask_mode, false);
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}
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/* Emit binary operations. */
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static void
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emit_binop (unsigned icode, rtx *ops, machine_mode mask_mode,
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machine_mode scalar_mode)
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void
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emit_nonvlmax_binop (unsigned icode, rtx dest, rtx src1, rtx src2, rtx len,
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machine_mode mask_mode, machine_mode scalar_mode)
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{
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insn_expander<9> e;
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machine_mode mode = GET_MODE (ops[0]);
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e.add_output_operand (ops[0], mode);
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e.add_all_one_mask_operand (mask_mode);
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e.add_vundef_operand (mode);
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if (VECTOR_MODE_P (GET_MODE (ops[1])))
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e.add_input_operand (ops[1], GET_MODE (ops[1]));
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else
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e.add_input_operand (ops[1], scalar_mode);
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if (VECTOR_MODE_P (GET_MODE (ops[2])))
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e.add_input_operand (ops[2], GET_MODE (ops[2]));
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else
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e.add_input_operand (ops[2], scalar_mode);
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rtx vlmax = gen_reg_rtx (Pmode);
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emit_vlmax_vsetvl (mode, vlmax);
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e.add_input_operand (vlmax, Pmode);
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e.add_policy_operand (get_prefer_tail_policy (), get_prefer_mask_policy ());
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e.add_avl_type_operand (avl_type::VLMAX);
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e.expand ((enum insn_code) icode, false);
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emit_pred_binop (icode, NULL_RTX, dest, src1, src2, len, mask_mode,
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scalar_mode, len ? false : true);
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}
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/* Emit vid.v instruction. */
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static void
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emit_index_op (rtx target, machine_mode mask_mode)
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emit_index_op (rtx dest, machine_mode mask_mode)
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{
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insn_expander<7> e;
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machine_mode mode = GET_MODE (target);
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e.add_output_operand (target, mode);
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e.add_all_one_mask_operand (mask_mode);
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e.add_vundef_operand (mode);
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rtx vlmax = gen_reg_rtx (Pmode);
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emit_vlmax_vsetvl (mode, vlmax);
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e.add_input_operand (vlmax, Pmode);
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e.add_policy_operand (get_prefer_tail_policy (), get_prefer_mask_policy ());
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e.add_avl_type_operand (avl_type::VLMAX);
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e.expand (code_for_pred_series (mode), false);
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e.set_dest_and_mask (NULL, dest, mask_mode);
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e.set_len_and_policy (NULL, true);
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e.expand (code_for_pred_series (GET_MODE (dest)), false);
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}
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/* Expand series const vector. */
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@ -324,15 +344,15 @@ expand_vec_series (rtx dest, rtx base, rtx step)
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/* Emit logical left shift operation. */
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int shift = exact_log2 (INTVAL (step));
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rtx shift_amount = gen_int_mode (shift, Pmode);
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rtx ops[3] = {step_adj, vid, shift_amount};
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insn_code icode = code_for_pred_scalar (ASHIFT, mode);
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emit_binop (icode, ops, mask_mode, Pmode);
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emit_nonvlmax_binop (icode, step_adj, vid, shift_amount,
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NULL, mask_mode, Pmode);
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}
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else
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{
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rtx ops[3] = {step_adj, vid, step};
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insn_code icode = code_for_pred_scalar (MULT, mode);
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emit_binop (icode, ops, mask_mode, inner_mode);
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emit_nonvlmax_binop (icode, step_adj, vid, step,
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NULL, mask_mode, inner_mode);
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}
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}
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@ -346,9 +366,9 @@ expand_vec_series (rtx dest, rtx base, rtx step)
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else
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{
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rtx result = gen_reg_rtx (mode);
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rtx ops[3] = {result, step_adj, base};
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insn_code icode = code_for_pred_scalar (PLUS, mode);
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emit_binop (icode, ops, mask_mode, inner_mode);
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emit_nonvlmax_binop (icode, result, step_adj, base,
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NULL, mask_mode, inner_mode);
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emit_move_insn (dest, result);
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}
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}
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