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h8300.c (output_simode_bld): Handle H8/300 and H8/300[HS] separately.

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* config/h8300/h8300.c (output_simode_bld): Handle H8/300 and
	H8/300[HS] separately.
	* config/h8300/h8300.md: Remove the early clobber constraint
	from bit field patterns.

From-SVN: r49995
This commit is contained in:
Kazu Hirata 2002-02-23 14:17:25 +00:00 • committed by Kazu Hirata
parent 35dad9f1bc
commit 6be580c7b5
3 changed files with 32 additions and 12 deletions
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7
gcc/ChangeLog
View file

@ -1,3 +1,10 @@
2002-02-23 Kazu Hirata <kazu@hxi.com>
* config/h8300/h8300.c (output_simode_bld): Handle H8/300 and
H8/300[HS] separately.
* config/h8300/h8300.md: Remove the early clobber constraint
from bit field patterns.
2002-02-23 Kazu Hirata <kazu@hxi.com>
* config/h8300/h8300.md (mulqihi3): Tighten predicates to

33
gcc/config/h8300/h8300.c
View file

@ -3120,18 +3120,31 @@ output_simode_bld (bild, operands)
int bild;
rtx operands[];
{
/* Clear the destination register. */
if (TARGET_H8300H || TARGET_H8300S)
output_asm_insn ("sub.l\t%S0,%S0", operands);
else
output_asm_insn ("sub.w\t%e0,%e0\n\tsub.w\t%f0,%f0", operands);
if (TARGET_H8300)
{
/* Clear the destination register. */
output_asm_insn ("sub.w\t%e0,%e0\n\tsub.w\t%f0,%f0", operands);
/* Now output the bit load or bit inverse load, and store it in
the destination. */
if (bild)
output_asm_insn ("bild\t%Z2,%Y1\n\tbst\t#0,%w0", operands);
/* Now output the bit load or bit inverse load, and store it in
the destination. */
if (bild)
output_asm_insn ("bild\t%Z2,%Y1", operands);
else
output_asm_insn ("bld\t%Z2,%Y1", operands);
output_asm_insn ("bst\t#0,%w0", operands);
}
else
output_asm_insn ("bld\t%Z2,%Y1\n\tbst\t#0,%w0", operands);
{
/* Output the bit load or bit inverse load. */
if (bild)
output_asm_insn ("bild\t%Z2,%Y1", operands);
else
output_asm_insn ("bld\t%Z2,%Y1", operands);
/* Clear the destination register and perform the bit store. */
output_asm_insn ("xor.l\t%S0,%S0\n\tbst\t#0,%w0", operands);
}
/* All done. */
return "";

4
gcc/config/h8300/h8300.md
View file

@ -2031,7 +2031,7 @@
(set_attr "length" "6")])
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=&r")
[(set (match_operand:SI 0 "register_operand" "=r")
(zero_extract:SI (match_operand:SI 1 "register_operand" "r")
(const_int 1)
(match_operand 2 "const_int_operand" "n")))]
@ -2059,7 +2059,7 @@
(set_attr "length" "6")])
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=&r")
[(set (match_operand:SI 0 "register_operand" "=r")
(zero_extract:SI (xor:SI (match_operand:SI 1 "register_operand" "r")
(match_operand 3 "const_int_operand" "n"))
(const_int 1)