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RISC-V: Fix incorrect mode tieable which cause ICE in RA[PR111296]

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This patch fix incorrect mode tieable between DI and V2SI which cause ICE
in RA.

gcc/ChangeLog:

	PR target/111296
	* config/riscv/riscv.cc (riscv_modes_tieable_p): Fix incorrect mode
	tieable for RVV modes.

gcc/testsuite/ChangeLog:

	PR target/111296
	* g++.target/riscv/rvv/base/pr111296.C: New test.
This commit is contained in:
Juzhe-Zhong 2023-09-06 22:28:03 +08:00 • committed by Pan Li
parent 1b4c70d427
commit 6b96de22d6
2 changed files with 23 additions and 0 deletions
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5
gcc/config/riscv/riscv.cc
View file

@ -7648,6 +7648,11 @@ riscv_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
static bool
riscv_modes_tieable_p (machine_mode mode1, machine_mode mode2)
{
/* We don't allow different REG_CLASS modes tieable since it
will cause ICE in register allocation (RA).
E.g. V2SI and DI are not tieable. */
if (riscv_v_ext_mode_p (mode1) != riscv_v_ext_mode_p (mode2))
return false;
return (mode1 == mode2
|| !(GET_MODE_CLASS (mode1) == MODE_FLOAT
&& GET_MODE_CLASS (mode2) == MODE_FLOAT));

18
gcc/testsuite/g++.target/riscv/rvv/base/pr111296.C Normal file
View file

@ -0,0 +1,18 @@
/* { dg-do compile } */
/* { dg-options "-std=c++03 -march=rv64gcv -mabi=lp64d -Ofast -ftree-vectorize --param=riscv-autovec-preference=scalable" } */
struct a
{
int b;
int c;
};
int d;
a
e ()
{
a f;
int g = d - 1, h = d / 2 - 1;
f.b = g;
f.c = h;
return f;
}