AVX10.2 ymm rounding: Support vcvtpd2{,u}{dq,qq} intrins
gcc/ChangeLog: * config/i386/avx10_2roundingintrin.h: Add new intrins. * config/i386/i386-builtin-types.def: Add new DEF_FUNCTION_TYPE. * config/i386/i386-builtin.def (BDESC): Add new builtins. * config/i386/i386-expand.cc (ix86_expand_round_builtin): Handle V4DI_FTYPE_V4DF_V4DI_UQI_INT, V4SI_FTYPE_V4DF_V4SI_UQI_INT. * config/i386/sse.md: (avx_cvtpd2dq256<mask_name>): Change name to avx_cvtpd2dq256<mask_name><round_name> and extend pattern to generate 256bit insns. (fixuns_notrunc<mode><si2dfmodelower>2<mask_name><round_name>): Add round_mode_condition. * config/i386/subst.md (round_pd2udqsuff): New iterator. gcc/testsuite/ChangeLog: * gcc.target/i386/avx-1.c: Add new builtin test. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-23.c: Ditto. * gcc.target/i386/sse-14.c: Add new macro test. * gcc.target/i386/sse-22.c: Ditto. * gcc.target/i386/avx10_2-rounding-1.c: Add test.
This commit is contained in:
Hu, Lin1
Haochen Jiang
parent
85e874d195
commit
508ac49e1a
12 changed files with 303 additions and 6 deletions
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@ -348,6 +348,144 @@ _mm256_maskz_cvt_roundpd_ps (__mmask8 __U, __m256d __A, const int __R)
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(__mmask8) __U,
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__R);
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}
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extern __inline __m128i
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__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
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_mm256_cvt_roundpd_epi32 (__m256d __A, const int __R)
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{
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return
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(__m128i) __builtin_ia32_cvtpd2dq256_mask_round ((__v4df) __A,
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(__v4si)
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_mm_undefined_si128 (),
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(__mmask8) -1,
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__R);
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}
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extern __inline __m128i
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__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
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_mm256_mask_cvt_roundpd_epi32 (__m128i __W, __mmask8 __U, __m256d __A,
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const int __R)
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{
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return (__m128i) __builtin_ia32_cvtpd2dq256_mask_round ((__v4df) __A,
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(__v4si) __W,
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(__mmask8) __U,
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__R);
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}
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extern __inline __m128i
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__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
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_mm256_maskz_cvt_roundpd_epi32 (__mmask8 __U, __m256d __A, const int __R)
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{
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return (__m128i) __builtin_ia32_cvtpd2dq256_mask_round ((__v4df) __A,
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(__v4si)
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_mm_setzero_si128 (),
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(__mmask8) __U,
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__R);
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}
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extern __inline __m256i
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__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
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_mm256_cvt_roundpd_epi64 (__m256d __A, const int __R)
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{
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return
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(__m256i) __builtin_ia32_cvtpd2qq256_mask_round ((__v4df) __A,
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(__v4di)
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_mm256_setzero_si256 (),
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(__mmask8) -1,
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__R);
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}
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extern __inline __m256i
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__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
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_mm256_mask_cvt_roundpd_epi64 (__m256i __W, __mmask8 __U, __m256d __A,
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const int __R)
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{
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return (__m256i) __builtin_ia32_cvtpd2qq256_mask_round ((__v4df) __A,
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(__v4di) __W,
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(__mmask8) __U,
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__R);
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}
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extern __inline __m256i
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__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
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_mm256_maskz_cvt_roundpd_epi64 (__mmask8 __U, __m256d __A, const int __R)
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{
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return
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(__m256i) __builtin_ia32_cvtpd2qq256_mask_round ((__v4df) __A,
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(__v4di)
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_mm256_setzero_si256 (),
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(__mmask8) __U,
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__R);
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}
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extern __inline __m128i
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__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
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_mm256_cvt_roundpd_epu32 (__m256d __A, const int __R)
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{
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return
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(__m128i) __builtin_ia32_cvtpd2udq256_mask_round ((__v4df) __A,
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(__v4si)
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_mm_undefined_si128 (),
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(__mmask8) -1,
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__R);
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}
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extern __inline __m128i
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__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
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_mm256_mask_cvt_roundpd_epu32 (__m128i __W, __mmask8 __U, __m256d __A,
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const int __R)
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{
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return (__m128i) __builtin_ia32_cvtpd2udq256_mask_round ((__v4df) __A,
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(__v4si) __W,
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(__mmask8) __U,
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__R);
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}
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extern __inline __m128i
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__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
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_mm256_maskz_cvt_roundpd_epu32 (__mmask8 __U, __m256d __A, const int __R)
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{
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return (__m128i) __builtin_ia32_cvtpd2udq256_mask_round ((__v4df) __A,
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(__v4si)
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_mm_setzero_si128 (),
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(__mmask8) __U,
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__R);
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}
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extern __inline __m256i
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__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
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_mm256_cvt_roundpd_epu64 (__m256d __A, const int __R)
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{
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return
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(__m256i) __builtin_ia32_cvtpd2uqq256_mask_round ((__v4df) __A,
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(__v4di)
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_mm256_setzero_si256 (),
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(__mmask8) -1,
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__R);
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}
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extern __inline __m256i
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__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
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_mm256_mask_cvt_roundpd_epu64 (__m256i __W, __mmask8 __U, __m256d __A,
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const int __R)
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{
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return (__m256i) __builtin_ia32_cvtpd2uqq256_mask_round ((__v4df) __A,
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(__v4di) __W,
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(__mmask8) __U,
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__R);
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}
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extern __inline __m256i
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__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
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_mm256_maskz_cvt_roundpd_epu64 (__mmask8 __U, __m256d __A, const int __R)
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{
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return
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(__m256i) __builtin_ia32_cvtpd2uqq256_mask_round ((__v4df) __A,
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(__v4di)
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_mm256_setzero_si256 (),
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(__mmask8) __U,
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__R);
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}
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#else
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#define _mm256_add_round_pd(A, B, R) \
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((__m256d) __builtin_ia32_addpd256_mask_round ((__v4df) (A), \
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@ -537,6 +675,86 @@ _mm256_maskz_cvt_roundpd_ps (__mmask8 __U, __m256d __A, const int __R)
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(_mm_setzero_ps ()), \
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(__mmask8) (U), \
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(R)))
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#define _mm256_cvt_roundpd_epi32(A, R) \
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((__m128i) __builtin_ia32_cvtpd2dq256_mask_round ((__v4df) (A), \
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(__v4si) \
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(_mm_undefined_si128 ()), \
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(__mmask8) (-1), \
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(R)))
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#define _mm256_mask_cvt_roundpd_epi32(W, U, A, R) \
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((__m128i) __builtin_ia32_cvtpd2dq256_mask_round ((__v4df) (A), \
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(__v4si) (W), \
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(__mmask8) (U), \
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(R)))
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#define _mm256_maskz_cvt_roundpd_epi32(U, A, R)\
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((__m128i) __builtin_ia32_cvtpd2dq256_mask_round ((__v4df) (A), \
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(__v4si) \
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(_mm_setzero_si128 ()), \
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(__mmask8) (U), \
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(R)))
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#define _mm256_cvt_roundpd_epi64(A, R) \
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((__m256i) __builtin_ia32_cvtpd2qq256_mask_round ((__v4df) (A), \
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(__v4di) \
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(_mm256_setzero_si256 ()), \
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(__mmask8) (-1), \
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(R)))
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#define _mm256_mask_cvt_roundpd_epi64(W, U, A, R) \
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((__m256i) __builtin_ia32_cvtpd2qq256_mask_round ((__v4df) (A), \
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(__v4di) (W), \
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(__mmask8) (U), \
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(R)))
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#define _mm256_maskz_cvt_roundpd_epi64(U, A, R) \
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((__m256i) __builtin_ia32_cvtpd2qq256_mask_round ((__v4df) (A), \
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(__v4di) \
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(_mm256_setzero_si256 ()), \
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(__mmask8) (U), \
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(R)))
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#define _mm256_cvt_roundpd_epu32(A, R) \
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((__m128i) __builtin_ia32_cvtpd2udq256_mask_round ((__v4df) (A), \
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(__v4si) \
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(_mm_undefined_si128 ()), \
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(__mmask8) (-1), \
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(R)))
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#define _mm256_mask_cvt_roundpd_epu32(W, U, A, R) \
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((__m128i) __builtin_ia32_cvtpd2udq256_mask_round ((__v4df) (A), \
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(__v4si) (W), \
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(__mmask8) (U), \
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(R)))
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#define _mm256_maskz_cvt_roundpd_epu32(U, A, R) \
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((__m128i) __builtin_ia32_cvtpd2udq256_mask_round ((__v4df) (A), \
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(__v4si) \
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(_mm_setzero_si128 ()), \
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(__mmask8) (U), \
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(R)))
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#define _mm256_cvt_roundpd_epu64(A, R) \
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((__m256i) __builtin_ia32_cvtpd2uqq256_mask_round ((__v4df) (A), \
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(__v4di) \
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(_mm256_setzero_si256 ()),\
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(__mmask8) (-1), \
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(R)))
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#define _mm256_mask_cvt_roundpd_epu64(W, U, A, R) \
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((__m256i) __builtin_ia32_cvtpd2uqq256_mask_round ((__v4df) (A), \
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(__v4di) (W), \
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(__mmask8) (U), \
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(R)))
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#define _mm256_maskz_cvt_roundpd_epu64(U, A, R) \
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((__m256i) __builtin_ia32_cvtpd2uqq256_mask_round ((__v4df) (A), \
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(__v4di) \
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(_mm256_setzero_si256 ()),\
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(__mmask8) (U), \
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(R)))
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#endif
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#ifdef __DISABLE_AVX10_2_256__
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@ -1425,3 +1425,5 @@ DEF_FUNCTION_TYPE (V8HF, V8SI, V8HF, UQI, INT)
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DEF_FUNCTION_TYPE (V8SF, V8SI, V8SF, UQI, INT)
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DEF_FUNCTION_TYPE (V8HF, V4DF, V8HF, UQI, INT)
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DEF_FUNCTION_TYPE (V4SF, V4DF, V4SF, UQI, INT)
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DEF_FUNCTION_TYPE (V4SI, V4DF, V4SI, UQI, INT)
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DEF_FUNCTION_TYPE (V4DI, V4DF, V4DI, UQI, INT)
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@ -3329,6 +3329,10 @@ BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx512fp16_vcvtdq2ph_v8si_mask_
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BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_floatv8siv8sf2_mask_round, "__builtin_ia32_cvtdq2ps256_mask_round", IX86_BUILTIN_VCVTDQ2PS256_MASK_ROUND, UNKNOWN, (int) V8SF_FTYPE_V8SI_V8SF_UQI_INT)
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BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx512fp16_vcvtpd2ph_v4df_mask_round, "__builtin_ia32_vcvtpd2ph256_mask_round", IX86_BUILTIN_VCVTPD2PH256_MASK_ROUND, UNKNOWN, (int) V8HF_FTYPE_V4DF_V8HF_UQI_INT)
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BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx_cvtpd2ps256_mask_round, "__builtin_ia32_cvtpd2ps256_mask_round", IX86_BUILTIN_CVTPD2PS256_MASK_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4DF_V4SF_UQI_INT)
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BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx_cvtpd2dq256_mask_round, "__builtin_ia32_cvtpd2dq256_mask_round", IX86_BUILTIN_CVTPD2DQ256_MASK_ROUND, UNKNOWN, (int) V4SI_FTYPE_V4DF_V4SI_UQI_INT)
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BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_fix_notruncv4dfv4di2_mask_round, "__builtin_ia32_cvtpd2qq256_mask_round", IX86_BUILTIN_CVTPD2QQ256_MASK_ROUND, UNKNOWN, (int) V4DI_FTYPE_V4DF_V4DI_UQI_INT)
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BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_fixuns_notruncv4dfv4si2_mask_round, "__builtin_ia32_cvtpd2udq256_mask_round", IX86_BUILTIN_CVTPD2UDQ256_MASK_ROUND, UNKNOWN, (int) V4SI_FTYPE_V4DF_V4SI_UQI_INT)
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BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_fixuns_notruncv4dfv4di2_mask_round, "__builtin_ia32_cvtpd2uqq256_mask_round", IX86_BUILTIN_CVTPD2UQQ256_MASK_ROUND, UNKNOWN, (int) V4DI_FTYPE_V4DF_V4DI_UQI_INT)
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BDESC_END (ROUND_ARGS, MULTI_ARG)
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@ -12402,7 +12402,9 @@ ix86_expand_round_builtin (const struct builtin_description *d,
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case V8DF_FTYPE_V8SF_V8DF_QI_INT:
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case V16SF_FTYPE_V16HI_V16SF_HI_INT:
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case V8SF_FTYPE_V8SI_V8SF_UQI_INT:
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case V4DI_FTYPE_V4DF_V4DI_UQI_INT:
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case V2DF_FTYPE_V2DF_V2DF_V2DF_INT:
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case V4SI_FTYPE_V4DF_V4SI_UQI_INT:
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case V4SF_FTYPE_V4DF_V4SF_UQI_INT:
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case V4SF_FTYPE_V4SF_V4SF_V4SF_INT:
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case V8HF_FTYPE_V8DI_V8HF_UQI_INT:
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@ -9141,12 +9141,13 @@
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(set_attr "prefix" "evex")
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(set_attr "mode" "OI")])
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(define_insn "avx_cvtpd2dq256<mask_name>"
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(define_insn "avx_cvtpd2dq256<mask_name><round_name>"
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[(set (match_operand:V4SI 0 "register_operand" "=v")
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(unspec:V4SI [(match_operand:V4DF 1 "nonimmediate_operand" "vm")]
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(unspec:V4SI [(match_operand:V4DF 1 "<round_nimm_predicate>" "<round_constraint>")]
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UNSPEC_FIX_NOTRUNC))]
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"TARGET_AVX && <mask_avx512vl_condition>"
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"vcvtpd2dq{y}\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
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"TARGET_AVX && <mask_avx512vl_condition>
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&& (!<round_applied> || TARGET_AVX10_2_256)"
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"vcvtpd2dq<round_suff>\t{<round_mask_op2>%1, %0<mask_operand2>|%0<mask_operand2>, %1<round_mask_op2>}"
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[(set_attr "type" "ssecvt")
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(set_attr "prefix" "<mask_prefix>")
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(set_attr "mode" "OI")])
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@ -9236,8 +9237,8 @@
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(unspec:<si2dfmode>
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[(match_operand:VF2_512_256VL 1 "nonimmediate_operand" "<round_constraint>")]
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UNSPEC_UNSIGNED_FIX_NOTRUNC))]
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"TARGET_AVX512F"
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"vcvtpd2udq<pd2udqsuff>\t{<round_mask_op2>%1, %0<mask_operand2>|%0<mask_operand2>, %1<round_mask_op2>}"
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"TARGET_AVX512F && <round_mode_condition>"
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"vcvtpd2udq<round_pd2udqsuff>\t{<round_mask_op2>%1, %0<mask_operand2>|%0<mask_operand2>, %1<round_mask_op2>}"
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[(set_attr "type" "ssecvt")
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(set_attr "prefix" "evex")
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(set_attr "mode" "<sseinsnmode>")])
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@ -199,6 +199,7 @@
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(define_subst_attr "round_constraint" "round" "vm" "v")
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(define_subst_attr "round_suff" "round" "{y}" "")
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(define_subst_attr "round_qq2phsuff" "round" "<qq2phsuff>" "")
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(define_subst_attr "round_pd2udqsuff" "round" "<pd2udqsuff>" "")
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(define_subst_attr "bcst_round_constraint" "round" "vmBr" "v")
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(define_subst_attr "round_constraint2" "round" "m" "v")
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(define_subst_attr "round_constraint3" "round" "rm" "r")
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@ -853,6 +853,10 @@
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#define __builtin_ia32_cvtdq2ps256_mask_round(A, B, C, D) __builtin_ia32_cvtdq2ps256_mask_round(A, B, C, 8)
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#define __builtin_ia32_vcvtpd2ph256_mask_round(A, B, C, D) __builtin_ia32_vcvtpd2ph256_mask_round(A, B, C, 8)
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#define __builtin_ia32_cvtpd2ps256_mask_round(A, B, C, D) __builtin_ia32_cvtpd2ps256_mask_round(A, B, C, 8)
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#define __builtin_ia32_cvtpd2dq256_mask_round(A, B, C, D) __builtin_ia32_cvtpd2dq256_mask_round(A, B, C, 8)
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#define __builtin_ia32_cvtpd2qq256_mask_round(A, B, C, D) __builtin_ia32_cvtpd2qq256_mask_round(A, B, C, 8)
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#define __builtin_ia32_cvtpd2udq256_mask_round(A, B, C, D) __builtin_ia32_cvtpd2udq256_mask_round(A, B, C, 8)
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#define __builtin_ia32_cvtpd2uqq256_mask_round(A, B, C, D) __builtin_ia32_cvtpd2uqq256_mask_round(A, B, C, 8)
|
||||
|
||||
#include <wmmintrin.h>
|
||||
#include <immintrin.h>
|
||||
|
|
|
|||
|
|
@ -27,10 +27,23 @@
|
|||
/* { dg-final { scan-assembler-times "vcvtpd2ps\[ \\t\]+\[^\n\]*\{rn-sae\}\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "vcvtpd2ps\[ \\t\]+\[^\n\]*\{rd-sae\}\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "vcvtpd2ps\[ \\t\]+\[^\n\]*\{rz-sae\}\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "vcvtpd2dq\[ \\t\]+\[^\n\]*\{rn-sae\}\[^\n\]*%ymm\[0-9\]+\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "vcvtpd2dq\[ \\t\]+\[^\n\]*\{ru-sae\}\[^\n\]*%ymm\[0-9\]+\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "vcvtpd2dq\[ \\t\]+\[^\n\]*\{rz-sae\}\[^\n\]*%ymm\[0-9\]+\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "vcvtpd2qq\[ \\t\]+\[^\n\]*\{rn-sae\}\[^\{\n\]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "vcvtpd2qq\[ \\t\]+\[^\n\]*\{ru-sae\}\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "vcvtpd2qq\[ \\t\]+\[^\n\]*\{rz-sae\}\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "vcvtpd2udq\[ \\t\]+\[^\n\]*\{rn-sae\}\[^\n\]*%ymm\[0-9\]+\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "vcvtpd2udq\[ \\t\]+\[^\n\]*\{ru-sae\}\[^\n\]*%ymm\[0-9\]+\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "vcvtpd2udq\[ \\t\]+\[^\n\]*\{rz-sae\}\[^\n\]*%ymm\[0-9\]+\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "vcvtpd2uqq\[ \\t\]+\[^\n\]*\{rn-sae\}\[^\{\n\]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "vcvtpd2uqq\[ \\t\]+\[^\n\]*\{rd-sae\}\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "vcvtpd2uqq\[ \\t\]+\[^\n\]*\{rz-sae\}\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */
|
||||
|
||||
#include <immintrin.h>
|
||||
|
||||
volatile __m128 hx;
|
||||
volatile __m128i hxi;
|
||||
volatile __m128h hxh;
|
||||
volatile __m256 x;
|
||||
volatile __m256d xd;
|
||||
|
|
@ -92,3 +105,23 @@ avx10_2_test_4 (void)
|
|||
hx = _mm256_mask_cvt_roundpd_ps (hx, 4, xd, _MM_FROUND_TO_NEG_INF | _MM_FROUND_NO_EXC);
|
||||
hx = _mm256_maskz_cvt_roundpd_ps (6, xd, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC);
|
||||
}
|
||||
|
||||
void extern
|
||||
avx10_2_test_5 (void)
|
||||
{
|
||||
hxi = _mm256_cvt_roundpd_epi32 (xd, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
|
||||
hxi = _mm256_mask_cvt_roundpd_epi32 (hxi, m8, xd, _MM_FROUND_TO_POS_INF | _MM_FROUND_NO_EXC);
|
||||
hxi = _mm256_maskz_cvt_roundpd_epi32 (m8, xd, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC);
|
||||
|
||||
xi = _mm256_cvt_roundpd_epi64 (xd, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
|
||||
xi = _mm256_mask_cvt_roundpd_epi64 (xi, m8, xd, _MM_FROUND_TO_POS_INF | _MM_FROUND_NO_EXC);
|
||||
xi = _mm256_maskz_cvt_roundpd_epi64 (m8, xd, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC);
|
||||
|
||||
hxi = _mm256_cvt_roundpd_epu32 (xd, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
|
||||
hxi = _mm256_mask_cvt_roundpd_epu32 (hxi, m8, xd, _MM_FROUND_TO_POS_INF | _MM_FROUND_NO_EXC);
|
||||
hxi = _mm256_maskz_cvt_roundpd_epu32 (m8, xd, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC);
|
||||
|
||||
xi = _mm256_cvt_roundpd_epu64 (xd, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
|
||||
xi = _mm256_mask_cvt_roundpd_epu64 (xi, m8, xd, _MM_FROUND_TO_NEG_INF | _MM_FROUND_NO_EXC);
|
||||
xi = _mm256_maskz_cvt_roundpd_epu64 (m8, xd, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -860,5 +860,9 @@
|
|||
#define __builtin_ia32_cvtdq2ps256_mask_round(A, B, C, D) __builtin_ia32_cvtdq2ps256_mask_round(A, B, C, 8)
|
||||
#define __builtin_ia32_vcvtpd2ph256_mask_round(A, B, C, D) __builtin_ia32_vcvtpd2ph256_mask_round(A, B, C, 8)
|
||||
#define __builtin_ia32_cvtpd2ps256_mask_round(A, B, C, D) __builtin_ia32_cvtpd2ps256_mask_round(A, B, C, 8)
|
||||
#define __builtin_ia32_cvtpd2dq256_mask_round(A, B, C, D) __builtin_ia32_cvtpd2dq256_mask_round(A, B, C, 8)
|
||||
#define __builtin_ia32_cvtpd2qq256_mask_round(A, B, C, D) __builtin_ia32_cvtpd2qq256_mask_round(A, B, C, 8)
|
||||
#define __builtin_ia32_cvtpd2udq256_mask_round(A, B, C, D) __builtin_ia32_cvtpd2udq256_mask_round(A, B, C, 8)
|
||||
#define __builtin_ia32_cvtpd2uqq256_mask_round(A, B, C, D) __builtin_ia32_cvtpd2uqq256_mask_round(A, B, C, 8)
|
||||
|
||||
#include <x86intrin.h>
|
||||
|
|
|
|||
|
|
@ -1025,6 +1025,10 @@ test_1 (_mm256_cvt_roundepi32_ph, __m128h, __m256i, 8)
|
|||
test_1 (_mm256_cvt_roundepi32_ps, __m256, __m256i, 9)
|
||||
test_1 (_mm256_cvt_roundpd_ph, __m128h, __m256d, 8)
|
||||
test_1 (_mm256_cvt_roundpd_ps, __m128, __m256d, 9)
|
||||
test_1 (_mm256_cvt_roundpd_epi32, __m128i, __m256d, 9)
|
||||
test_1 (_mm256_cvt_roundpd_epi64, __m256i, __m256d, 9)
|
||||
test_1 (_mm256_cvt_roundpd_epu32, __m128i, __m256d, 9)
|
||||
test_1 (_mm256_cvt_roundpd_epu64, __m256i, __m256d, 9)
|
||||
test_2 (_mm256_add_round_pd, __m256d, __m256d, __m256d, 9)
|
||||
test_2 (_mm256_add_round_ph, __m256h, __m256h, __m256h, 8)
|
||||
test_2 (_mm256_add_round_ps, __m256, __m256, __m256, 9)
|
||||
|
|
@ -1032,6 +1036,10 @@ test_2 (_mm256_maskz_cvt_roundepi32_ph, __m128h, __mmask8, __m256i, 8)
|
|||
test_2 (_mm256_maskz_cvt_roundepi32_ps, __m256, __mmask8, __m256i, 9)
|
||||
test_2 (_mm256_maskz_cvt_roundpd_ph, __m128h, __mmask8, __m256d, 8)
|
||||
test_2 (_mm256_maskz_cvt_roundpd_ps, __m128, __mmask8, __m256d, 9)
|
||||
test_2 (_mm256_maskz_cvt_roundpd_epi32, __m128i, __mmask8, __m256d, 9)
|
||||
test_2 (_mm256_maskz_cvt_roundpd_epi64, __m256i, __mmask8, __m256d, 9)
|
||||
test_2 (_mm256_maskz_cvt_roundpd_epu32, __m128i, __mmask8, __m256d, 9)
|
||||
test_2 (_mm256_maskz_cvt_roundpd_epu64, __m256i, __mmask8, __m256d, 9)
|
||||
test_2x (_mm256_cmp_round_pd_mask, __mmask8, __m256d, __m256d, 1, 8)
|
||||
test_2x (_mm256_cmp_round_ph_mask, __mmask16, __m256h, __m256h, 1, 8)
|
||||
test_2x (_mm256_cmp_round_ps_mask, __mmask8, __m256, __m256, 1, 8)
|
||||
|
|
@ -1042,6 +1050,10 @@ test_3 (_mm256_mask_cvt_roundepi32_ph, __m128h, __m128h, __mmask8, __m256i, 8)
|
|||
test_3 (_mm256_mask_cvt_roundepi32_ps, __m256, __m256, __mmask8, __m256i, 9)
|
||||
test_3 (_mm256_mask_cvt_roundpd_ph, __m128h, __m128h, __mmask8, __m256d, 8)
|
||||
test_3 (_mm256_mask_cvt_roundpd_ps, __m128, __m128, __mmask8, __m256d, 9)
|
||||
test_3 (_mm256_mask_cvt_roundpd_epi32, __m128i, __m128i, __mmask8, __m256d, 9)
|
||||
test_3 (_mm256_mask_cvt_roundpd_epu32, __m128i, __m128i, __mmask8, __m256d, 9)
|
||||
test_3 (_mm256_mask_cvt_roundpd_epi64, __m256i, __m256i, __mmask8, __m256d, 9)
|
||||
test_3 (_mm256_mask_cvt_roundpd_epu64, __m256i, __m256i, __mmask8, __m256d, 9)
|
||||
test_3x (_mm256_mask_cmp_round_pd_mask, __mmask8, __mmask8, __m256d, __m256d, 1, 8)
|
||||
test_3x (_mm256_mask_cmp_round_ph_mask, __mmask16, __mmask16, __m256h, __m256h, 1, 8)
|
||||
test_3x (_mm256_mask_cmp_round_ps_mask, __mmask8, __mmask8, __m256, __m256, 1, 8)
|
||||
|
|
|
|||
|
|
@ -1066,6 +1066,10 @@ test_1 (_mm256_cvt_roundepi32_ph, __m128h, __m256i, 8)
|
|||
test_1 (_mm256_cvt_roundepi32_ps, __m256, __m256i, 9)
|
||||
test_1 (_mm256_cvt_roundpd_ph, __m128h, __m256d, 8)
|
||||
test_1 (_mm256_cvt_roundpd_ps, __m128, __m256d, 9)
|
||||
test_1 (_mm256_cvt_roundpd_epi32, __m128i, __m256d, 9)
|
||||
test_1 (_mm256_cvt_roundpd_epi64, __m256i, __m256d, 9)
|
||||
test_1 (_mm256_cvt_roundpd_epu32, __m128i, __m256d, 9)
|
||||
test_1 (_mm256_cvt_roundpd_epu64, __m256i, __m256d, 9)
|
||||
test_2 (_mm256_add_round_pd, __m256d, __m256d, __m256d, 9)
|
||||
test_2 (_mm256_add_round_ph, __m256h, __m256h, __m256h, 8)
|
||||
test_2 (_mm256_add_round_ps, __m256, __m256, __m256, 9)
|
||||
|
|
@ -1073,6 +1077,10 @@ test_2 (_mm256_maskz_cvt_roundepi32_ph, __m128h, __mmask8, __m256i, 8)
|
|||
test_2 (_mm256_maskz_cvt_roundepi32_ps, __m256, __mmask8, __m256i, 9)
|
||||
test_2 (_mm256_maskz_cvt_roundpd_ph, __m128h, __mmask8, __m256d, 8)
|
||||
test_2 (_mm256_maskz_cvt_roundpd_ps, __m128, __mmask8, __m256d, 9)
|
||||
test_2 (_mm256_maskz_cvt_roundpd_epi32, __m128i, __mmask8, __m256d, 9)
|
||||
test_2 (_mm256_maskz_cvt_roundpd_epi64, __m256i, __mmask8, __m256d, 9)
|
||||
test_2 (_mm256_maskz_cvt_roundpd_epu32, __m128i, __mmask8, __m256d, 9)
|
||||
test_2 (_mm256_maskz_cvt_roundpd_epu64, __m256i, __mmask8, __m256d, 9)
|
||||
test_2x (_mm256_cmp_round_pd_mask, __mmask8, __m256d, __m256d, 1, 8)
|
||||
test_2x (_mm256_cmp_round_ph_mask, __mmask16, __m256h, __m256h, 1, 8)
|
||||
test_2x (_mm256_cmp_round_ps_mask, __mmask8, __m256, __m256, 1, 8)
|
||||
|
|
@ -1083,6 +1091,10 @@ test_3 (_mm256_mask_cvt_roundepi32_ph, __m128h, __m128h, __mmask8, __m256i, 8)
|
|||
test_3 (_mm256_mask_cvt_roundepi32_ps, __m256, __m256, __mmask8, __m256i, 9)
|
||||
test_3 (_mm256_mask_cvt_roundpd_ph, __m128h, __m128h, __mmask8, __m256d, 8)
|
||||
test_3 (_mm256_mask_cvt_roundpd_ps, __m128, __m128, __mmask8, __m256d, 9)
|
||||
test_3 (_mm256_mask_cvt_roundpd_epi32, __m128i, __m128i, __mmask8, __m256d, 9)
|
||||
test_3 (_mm256_mask_cvt_roundpd_epu32, __m128i, __m128i, __mmask8, __m256d, 9)
|
||||
test_3 (_mm256_mask_cvt_roundpd_epi64, __m256i, __m256i, __mmask8, __m256d, 9)
|
||||
test_3 (_mm256_mask_cvt_roundpd_epu64, __m256i, __m256i, __mmask8, __m256d, 9)
|
||||
test_3x (_mm256_mask_cmp_round_pd_mask, __mmask8, __mmask8, __m256d, __m256d, 1, 8)
|
||||
test_3x (_mm256_mask_cmp_round_ph_mask, __mmask16, __mmask16, __m256h, __m256h, 1, 8)
|
||||
test_3x (_mm256_mask_cmp_round_ps_mask, __mmask8, __mmask8, __m256, __m256, 1, 8)
|
||||
|
|
|
|||
|
|
@ -835,6 +835,10 @@
|
|||
#define __builtin_ia32_cvtdq2ps256_mask_round(A, B, C, D) __builtin_ia32_cvtdq2ps256_mask_round(A, B, C, 8)
|
||||
#define __builtin_ia32_vcvtpd2ph256_mask_round(A, B, C, D) __builtin_ia32_vcvtpd2ph256_mask_round(A, B, C, 8)
|
||||
#define __builtin_ia32_cvtpd2ps256_mask_round(A, B, C, D) __builtin_ia32_cvtpd2ps256_mask_round(A, B, C, 8)
|
||||
#define __builtin_ia32_cvtpd2dq256_mask_round(A, B, C, D) __builtin_ia32_cvtpd2dq256_mask_round(A, B, C, 8)
|
||||
#define __builtin_ia32_cvtpd2qq256_mask_round(A, B, C, D) __builtin_ia32_cvtpd2qq256_mask_round(A, B, C, 8)
|
||||
#define __builtin_ia32_cvtpd2udq256_mask_round(A, B, C, D) __builtin_ia32_cvtpd2udq256_mask_round(A, B, C, 8)
|
||||
#define __builtin_ia32_cvtpd2uqq256_mask_round(A, B, C, D) __builtin_ia32_cvtpd2uqq256_mask_round(A, B, C, 8)
|
||||
|
||||
#pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,fma,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,sha,xsavec,xsaves,clflushopt,clwb,mwaitx,clzero,pku,sgx,rdpid,gfni,vpclmulqdq,pconfig,wbnoinvd,enqcmd,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avxifma,avxvnniint8,avxneconvert,cmpccxadd,amx-fp16,prefetchi,raoint,amx-complex,avxvnniint16,sm3,sha512,sm4,avx10.2-512")
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue