AVX10.2 ymm rounding: Support vcvtdq2p{s,h} and vcvtpd2p{s,h} intrins
gcc/ChangeLog: * config/i386/avx10_2roundingintrin.h: Add new intrins. * config/i386/i386-builtin-types.def: Add new DEF_FUNCTION_TYPE. * config/i386/i386-builtin.def (BDESC): Add new builtins. * config/i386/i386-expand.cc (ix86_expand_round_builtin): Handle V8SF_FTYPE_V8SI_V8SF_UQI_INT, V4SF_FTYPE_V4DF_V4SF_UQI_INT, V8HF_FTYPE_V8SI_V8HF_UQI_INT, V8HF_FTYPE_V4DF_V8HF_UQI_INT. * config/i386/sse.md: (avx512fp16_vcvt<floatsuffix><sseintconvert>2ph_<mode><mask_name><round_name>): Add condition check. (avx512fp16_vcvtpd2ph_v4df_mask_round): New expand. (*avx512fp16_vcvt<castmode>2ph_<mode>_mask): Change name to avx512fp16_vcvt<castmode>2ph_<mode>_mask<round_name>_1 and extend pattern to generate 256bit insns. (avx_cvtpd2ps256<mask_name>): Change name to avx_cvtpd2ps256<mask_name><round_name> and extend pattern to generate 256bit insns. * config/i386/subst.md (round_applied): New condition. (round_suff): New iterator. (round_mode_condition): Add V32HI check for 512bit. (round_saeonly_mode_condition): Ditto. gcc/testsuite/ChangeLog: * gcc.target/i386/avx-1.c: Add new builtin test. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-23.c: Ditto. * gcc.target/i386/sse-14.c: Add new macro test. * gcc.target/i386/sse-22.c: Ditto. * gcc.target/i386/avx10_2-rounding-1.c: Add test.
This commit is contained in:
Hu, Lin1
Haochen Jiang
parent
e22e3af195
commit
85e874d195
12 changed files with 324 additions and 18 deletions
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@ -216,6 +216,138 @@ _mm256_mask_cmp_round_ps_mask (__mmask8 __U, __m256 __A, __m256 __B,
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(__mmask8) __U,
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__R);
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}
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extern __inline __m128h
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__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
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_mm256_cvt_roundepi32_ph (__m256i __A, const int __R)
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{
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return (__m128h) __builtin_ia32_vcvtdq2ph256_mask_round ((__v8si) __A,
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(__v8hf)
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_mm_setzero_ph (),
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(__mmask8) -1,
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__R);
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}
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extern __inline __m128h
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__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
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_mm256_mask_cvt_roundepi32_ph (__m128h __W, __mmask8 __U, __m256i __A,
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const int __R)
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{
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return (__m128h) __builtin_ia32_vcvtdq2ph256_mask_round ((__v8si) __A,
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(__v8hf) __W,
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(__mmask8) __U,
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__R);
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}
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extern __inline __m128h
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__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
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_mm256_maskz_cvt_roundepi32_ph (__mmask8 __U, __m256i __A, const int __R)
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{
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return (__m128h) __builtin_ia32_vcvtdq2ph256_mask_round ((__v8si) __A,
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(__v8hf)
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_mm_setzero_ph (),
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(__mmask8) __U,
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__R);
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}
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extern __inline __m256
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__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
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_mm256_cvt_roundepi32_ps (__m256i __A, const int __R)
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{
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return (__m256) __builtin_ia32_cvtdq2ps256_mask_round ((__v8si) __A,
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(__v8sf)
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_mm256_undefined_ps (),
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(__mmask8) -1,
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__R);
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}
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extern __inline __m256
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__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
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_mm256_mask_cvt_roundepi32_ps (__m256 __W, __mmask8 __U, __m256i __A,
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const int __R)
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{
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return (__m256) __builtin_ia32_cvtdq2ps256_mask_round ((__v8si) __A,
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(__v8sf) __W,
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(__mmask8) __U,
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__R);
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}
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extern __inline __m256
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__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
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_mm256_maskz_cvt_roundepi32_ps (__mmask8 __U, __m256i __A, const int __R)
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{
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return (__m256) __builtin_ia32_cvtdq2ps256_mask_round ((__v8si) __A,
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(__v8sf)
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_mm256_setzero_ps (),
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(__mmask8) __U,
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__R);
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}
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extern __inline __m128h
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__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
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_mm256_cvt_roundpd_ph (__m256d __A, const int __R)
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{
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return (__m128h) __builtin_ia32_vcvtpd2ph256_mask_round ((__v4df) __A,
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(__v8hf)
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_mm_setzero_ph (),
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(__mmask8) -1,
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__R);
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}
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extern __inline __m128h
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__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
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_mm256_mask_cvt_roundpd_ph (__m128h __W, __mmask8 __U, __m256d __A,
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const int __R)
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{
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return (__m128h) __builtin_ia32_vcvtpd2ph256_mask_round ((__v4df) __A,
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(__v8hf) __W,
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(__mmask8) __U,
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__R);
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}
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extern __inline __m128h
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__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
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_mm256_maskz_cvt_roundpd_ph (__mmask8 __U, __m256d __A, const int __R)
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{
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return (__m128h) __builtin_ia32_vcvtpd2ph256_mask_round ((__v4df) __A,
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(__v8hf)
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_mm_setzero_ph (),
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(__mmask8) __U,
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__R);
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}
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extern __inline __m128
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__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
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_mm256_cvt_roundpd_ps (__m256d __A, const int __R)
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{
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return (__m128) __builtin_ia32_cvtpd2ps256_mask_round ((__v4df) __A,
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(__v4sf)
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_mm_undefined_ps (),
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(__mmask8) -1,
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__R);
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}
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extern __inline __m128
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__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
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_mm256_mask_cvt_roundpd_ps (__m128 __W, __mmask8 __U, __m256d __A,
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const int __R)
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{
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return (__m128) __builtin_ia32_cvtpd2ps256_mask_round ((__v4df) __A,
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(__v4sf) __W,
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(__mmask8) __U,
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__R);
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}
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extern __inline __m128
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__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
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_mm256_maskz_cvt_roundpd_ps (__mmask8 __U, __m256d __A, const int __R)
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{
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return (__m128) __builtin_ia32_cvtpd2ps256_mask_round ((__v4df) __A,
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(__v4sf)
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_mm_setzero_ps (),
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(__mmask8) __U,
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__R);
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}
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#else
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#define _mm256_add_round_pd(A, B, R) \
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((__m256d) __builtin_ia32_addpd256_mask_round ((__v4df) (A), \
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@ -327,6 +459,84 @@ _mm256_mask_cmp_round_ps_mask (__mmask8 __U, __m256 __A, __m256 __B,
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(C), \
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(__mmask8) (U), \
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(R)))
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#define _mm256_cvt_roundepi32_ph(A, R) \
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((__m128h) __builtin_ia32_vcvtdq2ph256_mask_round ((__v8si) (A), \
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(__v8hf) \
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(_mm_setzero_ph ()), \
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(__mmask8) (-1), \
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(R)))
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#define _mm256_mask_cvt_roundepi32_ph(W, U, A, R) \
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((__m128h) __builtin_ia32_vcvtdq2ph256_mask_round ((__v8si) (A), \
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(__v8hf) (W), \
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(__mmask8) (U), \
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(R)))
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#define _mm256_maskz_cvt_roundepi32_ph(U, A, R) \
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((__m128h) __builtin_ia32_vcvtdq2ph256_mask_round ((__v8si) (A), \
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(__v8hf) \
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(_mm_setzero_ph ()), \
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(__mmask8) (U), \
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(R)))
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#define _mm256_cvt_roundepi32_ps(A, R) \
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((__m256) __builtin_ia32_cvtdq2ps256_mask_round ((__v8si) (A), \
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(__v8sf) \
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(_mm256_undefined_ps ()), \
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(__mmask8) (-1), \
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(R)))
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#define _mm256_mask_cvt_roundepi32_ps(W, U, A, R) \
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((__m256) __builtin_ia32_cvtdq2ps256_mask_round ((__v8si) (A), \
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(__v8sf) (W), \
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(__mmask8) (U), \
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(R)))
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#define _mm256_maskz_cvt_roundepi32_ps(U, A, R) \
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((__m256) __builtin_ia32_cvtdq2ps256_mask_round ((__v8si) (A), \
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(__v8sf) \
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(_mm256_setzero_ps ()), \
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(__mmask8) (U), \
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(R)))
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#define _mm256_cvt_roundpd_ph(A, R) \
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((__m128h) __builtin_ia32_vcvtpd2ph256_mask_round ((__v4df) (A), \
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(_mm_setzero_ph ()), \
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(__mmask8) (-1), \
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(R)))
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#define _mm256_mask_cvt_roundpd_ph(W, U, A, R) \
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((__m128h) __builtin_ia32_vcvtpd2ph256_mask_round ((__v4df) (A), \
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(__v8hf) (W), \
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(__mmask8) (U), \
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(R)))
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#define _mm256_maskz_cvt_roundpd_ph(U, A, R) \
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((__m128h) __builtin_ia32_vcvtpd2ph256_mask_round ((__v4df) (A), \
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(_mm_setzero_ph ()), \
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(__mmask8) (U), \
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(R)))
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#define _mm256_cvt_roundpd_ps(A, R) \
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((__m128) __builtin_ia32_cvtpd2ps256_mask_round ((__v4df) (A), \
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(__v4sf) \
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(_mm_undefined_ps ()), \
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(__mmask8) (-1), \
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(R)))
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#define _mm256_mask_cvt_roundpd_ps(W, U, A, R) \
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((__m128) __builtin_ia32_cvtpd2ps256_mask_round ((__v4df) (A), \
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(__v4sf) (W), \
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(__mmask8) (U), \
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(R)))
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#define _mm256_maskz_cvt_roundpd_ps(U, A, R) \
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((__m128) __builtin_ia32_cvtpd2ps256_mask_round ((__v4df) (A), \
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(__v4sf) \
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(_mm_setzero_ps ()), \
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(__mmask8) (U), \
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(R)))
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#endif
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#ifdef __DISABLE_AVX10_2_256__
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@ -1421,3 +1421,7 @@ DEF_FUNCTION_TYPE (V8SF, V8SF, V8SF, V8SF, UQI, INT)
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DEF_FUNCTION_TYPE (UQI, V4DF, V4DF, INT, UQI, INT)
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DEF_FUNCTION_TYPE (UHI, V16HF, V16HF, INT, UHI, INT)
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DEF_FUNCTION_TYPE (UQI, V8SF, V8SF, INT, UQI, INT)
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DEF_FUNCTION_TYPE (V8HF, V8SI, V8HF, UQI, INT)
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DEF_FUNCTION_TYPE (V8SF, V8SI, V8SF, UQI, INT)
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DEF_FUNCTION_TYPE (V8HF, V4DF, V8HF, UQI, INT)
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DEF_FUNCTION_TYPE (V4SF, V4DF, V4SF, UQI, INT)
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@ -3325,6 +3325,10 @@ BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_addv8sf3_mask_round, "__builtin
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BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx512vl_cmpv4df3_mask_round, "__builtin_ia32_cmppd256_mask_round", IX86_BUILTIN_CMPPD256_MASK_ROUND, UNKNOWN, (int) UQI_FTYPE_V4DF_V4DF_INT_UQI_INT)
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BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx512vl_cmpv16hf3_mask_round, "__builtin_ia32_cmpph256_mask_round", IX86_BUILTIN_CMPPH256_MASK_ROUND, UNKNOWN, (int) UHI_FTYPE_V16HF_V16HF_INT_UHI_INT)
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BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx512vl_cmpv8sf3_mask_round, "__builtin_ia32_cmpps256_mask_round", IX86_BUILTIN_CMPPS256_MASK_ROUND, UNKNOWN, (int) UQI_FTYPE_V8SF_V8SF_INT_UQI_INT)
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BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx512fp16_vcvtdq2ph_v8si_mask_round, "__builtin_ia32_vcvtdq2ph256_mask_round", IX86_BUILTIN_VCVTDQ2PH256_MASK_ROUND, UNKNOWN, (int) V8HF_FTYPE_V8SI_V8HF_UQI_INT)
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BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_floatv8siv8sf2_mask_round, "__builtin_ia32_cvtdq2ps256_mask_round", IX86_BUILTIN_VCVTDQ2PS256_MASK_ROUND, UNKNOWN, (int) V8SF_FTYPE_V8SI_V8SF_UQI_INT)
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BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx512fp16_vcvtpd2ph_v4df_mask_round, "__builtin_ia32_vcvtpd2ph256_mask_round", IX86_BUILTIN_VCVTPD2PH256_MASK_ROUND, UNKNOWN, (int) V8HF_FTYPE_V4DF_V8HF_UQI_INT)
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BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx_cvtpd2ps256_mask_round, "__builtin_ia32_cvtpd2ps256_mask_round", IX86_BUILTIN_CVTPD2PS256_MASK_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4DF_V4SF_UQI_INT)
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BDESC_END (ROUND_ARGS, MULTI_ARG)
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@ -12401,10 +12401,14 @@ ix86_expand_round_builtin (const struct builtin_description *d,
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case V16HF_FTYPE_V16SI_V16HF_UHI_INT:
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case V8DF_FTYPE_V8SF_V8DF_QI_INT:
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case V16SF_FTYPE_V16HI_V16SF_HI_INT:
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case V8SF_FTYPE_V8SI_V8SF_UQI_INT:
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case V2DF_FTYPE_V2DF_V2DF_V2DF_INT:
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case V4SF_FTYPE_V4DF_V4SF_UQI_INT:
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case V4SF_FTYPE_V4SF_V4SF_V4SF_INT:
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case V8HF_FTYPE_V8DI_V8HF_UQI_INT:
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case V8HF_FTYPE_V8DF_V8HF_UQI_INT:
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case V8HF_FTYPE_V8SI_V8HF_UQI_INT:
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case V8HF_FTYPE_V4DF_V8HF_UQI_INT:
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case V16HF_FTYPE_V16SF_V16HF_UHI_INT:
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case V8HF_FTYPE_V8HF_V8HF_V8HF_INT:
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nargs = 4;
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@ -7384,7 +7384,7 @@
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[(set (match_operand:<ssePHmode> 0 "register_operand" "=v")
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(any_float:<ssePHmode>
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(match_operand:VI2H_AVX512VL 1 "<round_nimm_predicate>" "<round_constraint>")))]
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"TARGET_AVX512FP16"
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"TARGET_AVX512FP16 && <round_mode_condition>"
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"vcvt<floatsuffix><sseintconvert>2ph<round_qq2phsuff>\t{<round_mask_op2>%1, %0<mask_operand2>|%0<mask_operand2>, %1<round_mask_op2>}"
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[(set_attr "type" "ssecvt")
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(set_attr "prefix" "evex")
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@ -7889,6 +7889,19 @@
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(set_attr "prefix" "evex")
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(set_attr "mode" "<sseinsnmode>")])
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(define_expand "avx512fp16_vcvtpd2ph_v4df_mask_round"
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[(match_operand:V8HF 0 "register_operand")
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(match_operand:V4DF 1 "register_operand")
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(match_operand:V8HF 2 "nonimm_or_0_operand")
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(match_operand:QI 3 "register_operand")
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(unspec [(match_operand:SI 4 "const_4_or_8_to_11_operand")] UNSPEC_EMBEDDED_ROUNDING)]
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"TARGET_AVX10_2_256"
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{
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emit_insn (gen_avx512fp16_vcvtpd2ph_v4df_mask_round_1 (
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operands[0], operands[1], operands[2], operands[3], CONST0_RTX (V4HFmode), operands[4]));
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DONE;
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})
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(define_expand "avx512fp16_vcvt<castmode>2ph_<mode>_mask"
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[(set (match_operand:V8HF 0 "register_operand" "=v")
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(vec_concat:V8HF
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@ -7904,20 +7917,20 @@
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"TARGET_AVX512FP16 && TARGET_AVX512VL"
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"operands[4] = CONST0_RTX (V4HFmode);")
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(define_insn "*avx512fp16_vcvt<castmode>2ph_<mode>_mask"
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(define_insn "avx512fp16_vcvt<castmode>2ph_<mode>_mask<round_name>_1"
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[(set (match_operand:V8HF 0 "register_operand" "=v")
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(vec_concat:V8HF
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(vec_merge:V4HF
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(float_truncate:V4HF
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(match_operand:VF4_128_8_256 1 "vector_operand" "vm"))
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(match_operand:VF4_128_8_256 1 "<round_nimm_predicate>" "<round_constraint>"))
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(vec_select:V4HF
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(match_operand:V8HF 2 "nonimm_or_0_operand" "0C")
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(parallel [(const_int 0) (const_int 1)
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(const_int 2) (const_int 3)]))
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(match_operand:QI 3 "register_operand" "Yk"))
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(match_operand:V4HF 4 "const0_operand")))]
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"TARGET_AVX512FP16 && TARGET_AVX512VL"
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"vcvt<castmode>2ph<ph2pssuffix><qq2phsuff>\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}"
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"TARGET_AVX512FP16 && TARGET_AVX512VL && <round_mode_condition>"
|
||||
"vcvt<castmode>2ph<ph2pssuffix><round_qq2phsuff>\t{<round_op5>%1, %0%{%3%}%N2|%0%{%3%}%N2, %1<round_op5>}"
|
||||
[(set_attr "type" "ssecvt")
|
||||
(set_attr "prefix" "evex")
|
||||
(set_attr "mode" "<sseinsnmode>")])
|
||||
|
|
@ -9813,12 +9826,13 @@
|
|||
(set_attr "prefix" "evex")
|
||||
(set_attr "mode" "V8SF")])
|
||||
|
||||
(define_insn "avx_cvtpd2ps256<mask_name>"
|
||||
(define_insn "avx_cvtpd2ps256<mask_name><round_name>"
|
||||
[(set (match_operand:V4SF 0 "register_operand" "=v")
|
||||
(float_truncate:V4SF
|
||||
(match_operand:V4DF 1 "nonimmediate_operand" "vm")))]
|
||||
"TARGET_AVX && <mask_avx512vl_condition>"
|
||||
"vcvtpd2ps{y}\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
|
||||
(match_operand:V4DF 1 "<round_nimm_predicate>" "<round_constraint>")))]
|
||||
"TARGET_AVX && <mask_avx512vl_condition>
|
||||
&& (!<round_applied> || TARGET_AVX10_2_256)"
|
||||
"vcvtpd2ps<round_suff>\t{<round_mask_op2>%1, %0<mask_operand2>|%0<mask_operand2>, %1<round_mask_op2>}"
|
||||
[(set_attr "type" "ssecvt")
|
||||
(set_attr "prefix" "maybe_evex")
|
||||
(set_attr "btver2_decode" "vector")
|
||||
|
|
|
|||
|
|
@ -197,6 +197,7 @@
|
|||
(define_subst_attr "round_sd_mask_op4" "round" "" "<round_sd_mask_operand4>")
|
||||
(define_subst_attr "round_sdc_mask_op4" "round" "" "<round_sdc_mask_operand4>")
|
||||
(define_subst_attr "round_constraint" "round" "vm" "v")
|
||||
(define_subst_attr "round_suff" "round" "{y}" "")
|
||||
(define_subst_attr "round_qq2phsuff" "round" "<qq2phsuff>" "")
|
||||
(define_subst_attr "bcst_round_constraint" "round" "vmBr" "v")
|
||||
(define_subst_attr "round_constraint2" "round" "m" "v")
|
||||
|
|
@ -209,6 +210,7 @@
|
|||
|| <MODE>mode == V8DFmode
|
||||
|| <MODE>mode == V8DImode
|
||||
|| <MODE>mode == V16SImode
|
||||
|| <MODE>mode == V32HImode
|
||||
|| <MODE>mode == V32HFmode)
|
||||
|| (TARGET_AVX10_2_256
|
||||
&& (<MODE>mode == V8SFmode
|
||||
|
|
@ -216,6 +218,7 @@
|
|||
|| <MODE>mode == V4DImode
|
||||
|| <MODE>mode == V8SImode
|
||||
|| <MODE>mode == V16HFmode)))")
|
||||
(define_subst_attr "round_applied" "round" "false" "true")
|
||||
|
||||
(define_subst_attr "round_modev4sf_condition" "round" "1" "(<MODE>mode == V4SFmode)")
|
||||
(define_subst_attr "round_codefor" "round" "*" "")
|
||||
|
|
@ -260,6 +263,7 @@
|
|||
|| <MODE>mode == V8DFmode
|
||||
|| <MODE>mode == V8DImode
|
||||
|| <MODE>mode == V16SImode
|
||||
|| <MODE>mode == V32HImode
|
||||
|| <MODE>mode == V32HFmode)
|
||||
|| (TARGET_AVX10_2_256
|
||||
&& (<MODE>mode == V8SFmode
|
||||
|
|
|
|||
|
|
@ -849,6 +849,10 @@
|
|||
#define __builtin_ia32_cmppd256_mask_round(A, B, C, D, E) __builtin_ia32_cmppd256_mask_round(A, B, 1, D, 8)
|
||||
#define __builtin_ia32_cmpph256_mask_round(A, B, C, D, E) __builtin_ia32_cmpph256_mask_round(A, B, 1, D, 8)
|
||||
#define __builtin_ia32_cmpps256_mask_round(A, B, C, D, E) __builtin_ia32_cmpps256_mask_round(A, B, 1, D, 8)
|
||||
#define __builtin_ia32_vcvtdq2ph256_mask_round(A, B, C, D) __builtin_ia32_vcvtdq2ph256_mask_round(A, B, C, 8)
|
||||
#define __builtin_ia32_cvtdq2ps256_mask_round(A, B, C, D) __builtin_ia32_cvtdq2ps256_mask_round(A, B, C, 8)
|
||||
#define __builtin_ia32_vcvtpd2ph256_mask_round(A, B, C, D) __builtin_ia32_vcvtpd2ph256_mask_round(A, B, C, 8)
|
||||
#define __builtin_ia32_cvtpd2ps256_mask_round(A, B, C, D) __builtin_ia32_cvtpd2ps256_mask_round(A, B, C, 8)
|
||||
|
||||
#include <wmmintrin.h>
|
||||
#include <immintrin.h>
|
||||
|
|
|
|||
|
|
@ -15,12 +15,27 @@
|
|||
/* { dg-final { scan-assembler-times "vcmpph\[ \\t\]+\[^\{\n\]*\\\$4\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%k\[0-9\]\{%k\[0-9\]\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "vcmpps\[ \\t\]+\[^\{\n\]*\{sae\}\[^\n\]*%ymm\[0-9\]+\[^\n^k\]*%k\[0-7\](?:\n|\[ \\t\]+#)" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "vcmpps\[ \\t\]+\[^\{\n\]*\{sae\}\[^\n\]*%ymm\[0-9\]+\[^\n^k\]*%k\[0-7\]\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "vcvtdq2phy\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "vcvtdq2ph\[ \\t\]+\{rn-sae\}\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "vcvtdq2ph\[ \\t\]+\{rz-sae\}\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "vcvtdq2ps\[ \\t\]+\[^\n\]*\{rn-sae\}\[^\{\n\]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "vcvtdq2ps\[ \\t\]+\[^\n\]*\{ru-sae\}\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "vcvtdq2ps\[ \\t\]+\[^\n\]*\{rz-sae\}\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "vcvtpd2phy\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "vcvtpd2ph\[ \\t\]+\{rn-sae\}\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "vcvtpd2ph\[ \\t\]+\{rz-sae\}\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "vcvtpd2ps\[ \\t\]+\[^\n\]*\{rn-sae\}\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "vcvtpd2ps\[ \\t\]+\[^\n\]*\{rd-sae\}\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "vcvtpd2ps\[ \\t\]+\[^\n\]*\{rz-sae\}\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */
|
||||
|
||||
#include <immintrin.h>
|
||||
|
||||
volatile __m128 hx;
|
||||
volatile __m128h hxh;
|
||||
volatile __m256 x;
|
||||
volatile __m256d xd;
|
||||
volatile __m256h xh;
|
||||
volatile __m256i xi;
|
||||
volatile __mmask8 m8;
|
||||
volatile __mmask16 m16;
|
||||
volatile __mmask32 m32;
|
||||
|
|
@ -39,15 +54,6 @@ avx10_2_test_1 (void)
|
|||
x = _mm256_add_round_ps (x, x, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
|
||||
x = _mm256_mask_add_round_ps (x, m16, x, x, _MM_FROUND_TO_POS_INF | _MM_FROUND_NO_EXC);
|
||||
x = _mm256_maskz_add_round_ps (m16, x, x, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC);
|
||||
|
||||
m8 = _mm256_cmp_round_pd_mask (xd, xd, _CMP_FALSE_OQ, _MM_FROUND_NO_EXC);
|
||||
m8 = _mm256_mask_cmp_round_pd_mask (m8, xd, xd, _CMP_FALSE_OQ, _MM_FROUND_NO_EXC);
|
||||
|
||||
m16 = _mm256_cmp_round_ph_mask (xh, xh, 3, 8);
|
||||
m16 = _mm256_mask_cmp_round_ph_mask (m16, xh, xh, 4, 4);
|
||||
|
||||
m8 = _mm256_cmp_round_ps_mask (x, x, _CMP_FALSE_OQ, _MM_FROUND_NO_EXC);
|
||||
m8 = _mm256_mask_cmp_round_ps_mask (m8, x, x, _CMP_FALSE_OQ, _MM_FROUND_NO_EXC);
|
||||
}
|
||||
|
||||
void extern
|
||||
|
|
@ -62,3 +68,27 @@ avx10_2_test_2 (void)
|
|||
m8 = _mm256_cmp_round_ps_mask (x, x, _CMP_FALSE_OQ, _MM_FROUND_NO_EXC);
|
||||
m8 = _mm256_mask_cmp_round_ps_mask (m8, x, x, _CMP_FALSE_OQ, _MM_FROUND_NO_EXC);
|
||||
}
|
||||
|
||||
void extern
|
||||
avx10_2_test_3 (void)
|
||||
{
|
||||
hxh = _mm256_cvt_roundepi32_ph (xi, 4);
|
||||
hxh = _mm256_mask_cvt_roundepi32_ph (hxh, m8, xi, 8);
|
||||
hxh = _mm256_maskz_cvt_roundepi32_ph (m8, xi, 11);
|
||||
|
||||
x = _mm256_cvt_roundepi32_ps (xi, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
|
||||
x = _mm256_mask_cvt_roundepi32_ps (x, m8, xi, _MM_FROUND_TO_POS_INF | _MM_FROUND_NO_EXC);
|
||||
x = _mm256_maskz_cvt_roundepi32_ps (m8, xi, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC);
|
||||
}
|
||||
|
||||
void extern
|
||||
avx10_2_test_4 (void)
|
||||
{
|
||||
hxh = _mm256_cvt_roundpd_ph (xd, 4);
|
||||
hxh = _mm256_mask_cvt_roundpd_ph (hxh, m8, xd, 8);
|
||||
hxh = _mm256_maskz_cvt_roundpd_ph (m8, xd, 11);
|
||||
|
||||
hx = _mm256_cvt_roundpd_ps (xd, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
|
||||
hx = _mm256_mask_cvt_roundpd_ps (hx, 4, xd, _MM_FROUND_TO_NEG_INF | _MM_FROUND_NO_EXC);
|
||||
hx = _mm256_maskz_cvt_roundpd_ps (6, xd, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -856,5 +856,9 @@
|
|||
#define __builtin_ia32_cmppd256_mask_round(A, B, C, D, E) __builtin_ia32_cmppd256_mask_round(A, B, 1, D, 8)
|
||||
#define __builtin_ia32_cmpph256_mask_round(A, B, C, D, E) __builtin_ia32_cmpph256_mask_round(A, B, 1, D, 8)
|
||||
#define __builtin_ia32_cmpps256_mask_round(A, B, C, D, E) __builtin_ia32_cmpps256_mask_round(A, B, 1, D, 8)
|
||||
#define __builtin_ia32_vcvtdq2ph256_mask_round(A, B, C, D) __builtin_ia32_vcvtdq2ph256_mask_round(A, B, C, 8)
|
||||
#define __builtin_ia32_cvtdq2ps256_mask_round(A, B, C, D) __builtin_ia32_cvtdq2ps256_mask_round(A, B, C, 8)
|
||||
#define __builtin_ia32_vcvtpd2ph256_mask_round(A, B, C, D) __builtin_ia32_vcvtpd2ph256_mask_round(A, B, C, 8)
|
||||
#define __builtin_ia32_cvtpd2ps256_mask_round(A, B, C, D) __builtin_ia32_cvtpd2ps256_mask_round(A, B, C, 8)
|
||||
|
||||
#include <x86intrin.h>
|
||||
|
|
|
|||
|
|
@ -1021,15 +1021,27 @@ test_2 (_mm512_gf2p8affine_epi64_epi8, __m512i, __m512i, __m512i, 1)
|
|||
test_3 (_mm_sm3rnds2_epi32, __m128i, __m128i, __m128i, __m128i, 1)
|
||||
|
||||
/* avx10_2roundingintrin.h */
|
||||
test_1 (_mm256_cvt_roundepi32_ph, __m128h, __m256i, 8)
|
||||
test_1 (_mm256_cvt_roundepi32_ps, __m256, __m256i, 9)
|
||||
test_1 (_mm256_cvt_roundpd_ph, __m128h, __m256d, 8)
|
||||
test_1 (_mm256_cvt_roundpd_ps, __m128, __m256d, 9)
|
||||
test_2 (_mm256_add_round_pd, __m256d, __m256d, __m256d, 9)
|
||||
test_2 (_mm256_add_round_ph, __m256h, __m256h, __m256h, 8)
|
||||
test_2 (_mm256_add_round_ps, __m256, __m256, __m256, 9)
|
||||
test_2 (_mm256_maskz_cvt_roundepi32_ph, __m128h, __mmask8, __m256i, 8)
|
||||
test_2 (_mm256_maskz_cvt_roundepi32_ps, __m256, __mmask8, __m256i, 9)
|
||||
test_2 (_mm256_maskz_cvt_roundpd_ph, __m128h, __mmask8, __m256d, 8)
|
||||
test_2 (_mm256_maskz_cvt_roundpd_ps, __m128, __mmask8, __m256d, 9)
|
||||
test_2x (_mm256_cmp_round_pd_mask, __mmask8, __m256d, __m256d, 1, 8)
|
||||
test_2x (_mm256_cmp_round_ph_mask, __mmask16, __m256h, __m256h, 1, 8)
|
||||
test_2x (_mm256_cmp_round_ps_mask, __mmask8, __m256, __m256, 1, 8)
|
||||
test_3 (_mm256_maskz_add_round_pd, __m256d, __mmask8, __m256d, __m256d, 9)
|
||||
test_3 (_mm256_maskz_add_round_ph, __m256h, __mmask16, __m256h, __m256h, 8)
|
||||
test_3 (_mm256_maskz_add_round_ps, __m256, __mmask8, __m256, __m256, 9)
|
||||
test_3 (_mm256_mask_cvt_roundepi32_ph, __m128h, __m128h, __mmask8, __m256i, 8)
|
||||
test_3 (_mm256_mask_cvt_roundepi32_ps, __m256, __m256, __mmask8, __m256i, 9)
|
||||
test_3 (_mm256_mask_cvt_roundpd_ph, __m128h, __m128h, __mmask8, __m256d, 8)
|
||||
test_3 (_mm256_mask_cvt_roundpd_ps, __m128, __m128, __mmask8, __m256d, 9)
|
||||
test_3x (_mm256_mask_cmp_round_pd_mask, __mmask8, __mmask8, __m256d, __m256d, 1, 8)
|
||||
test_3x (_mm256_mask_cmp_round_ph_mask, __mmask16, __mmask16, __m256h, __m256h, 1, 8)
|
||||
test_3x (_mm256_mask_cmp_round_ps_mask, __mmask8, __mmask8, __m256, __m256, 1, 8)
|
||||
|
|
|
|||
|
|
@ -1062,15 +1062,27 @@ test_1 ( __bextri_u64, unsigned long long, unsigned long long, 1)
|
|||
test_3 (_mm_sm3rnds2_epi32, __m128i, __m128i, __m128i, __m128i, 1)
|
||||
|
||||
/* avx10_2roundingintrin.h */
|
||||
test_1 (_mm256_cvt_roundepi32_ph, __m128h, __m256i, 8)
|
||||
test_1 (_mm256_cvt_roundepi32_ps, __m256, __m256i, 9)
|
||||
test_1 (_mm256_cvt_roundpd_ph, __m128h, __m256d, 8)
|
||||
test_1 (_mm256_cvt_roundpd_ps, __m128, __m256d, 9)
|
||||
test_2 (_mm256_add_round_pd, __m256d, __m256d, __m256d, 9)
|
||||
test_2 (_mm256_add_round_ph, __m256h, __m256h, __m256h, 8)
|
||||
test_2 (_mm256_add_round_ps, __m256, __m256, __m256, 9)
|
||||
test_2 (_mm256_maskz_cvt_roundepi32_ph, __m128h, __mmask8, __m256i, 8)
|
||||
test_2 (_mm256_maskz_cvt_roundepi32_ps, __m256, __mmask8, __m256i, 9)
|
||||
test_2 (_mm256_maskz_cvt_roundpd_ph, __m128h, __mmask8, __m256d, 8)
|
||||
test_2 (_mm256_maskz_cvt_roundpd_ps, __m128, __mmask8, __m256d, 9)
|
||||
test_2x (_mm256_cmp_round_pd_mask, __mmask8, __m256d, __m256d, 1, 8)
|
||||
test_2x (_mm256_cmp_round_ph_mask, __mmask16, __m256h, __m256h, 1, 8)
|
||||
test_2x (_mm256_cmp_round_ps_mask, __mmask8, __m256, __m256, 1, 8)
|
||||
test_3 (_mm256_maskz_add_round_pd, __m256d, __mmask8, __m256d, __m256d, 9)
|
||||
test_3 (_mm256_maskz_add_round_ph, __m256h, __mmask16, __m256h, __m256h, 8)
|
||||
test_3 (_mm256_maskz_add_round_ps, __m256, __mmask8, __m256, __m256, 9)
|
||||
test_3 (_mm256_mask_cvt_roundepi32_ph, __m128h, __m128h, __mmask8, __m256i, 8)
|
||||
test_3 (_mm256_mask_cvt_roundepi32_ps, __m256, __m256, __mmask8, __m256i, 9)
|
||||
test_3 (_mm256_mask_cvt_roundpd_ph, __m128h, __m128h, __mmask8, __m256d, 8)
|
||||
test_3 (_mm256_mask_cvt_roundpd_ps, __m128, __m128, __mmask8, __m256d, 9)
|
||||
test_3x (_mm256_mask_cmp_round_pd_mask, __mmask8, __mmask8, __m256d, __m256d, 1, 8)
|
||||
test_3x (_mm256_mask_cmp_round_ph_mask, __mmask16, __mmask16, __m256h, __m256h, 1, 8)
|
||||
test_3x (_mm256_mask_cmp_round_ps_mask, __mmask8, __mmask8, __m256, __m256, 1, 8)
|
||||
|
|
|
|||
|
|
@ -831,6 +831,10 @@
|
|||
#define __builtin_ia32_cmppd256_mask_round(A, B, C, D, E) __builtin_ia32_cmppd256_mask_round(A, B, 1, D, 8)
|
||||
#define __builtin_ia32_cmpph256_mask_round(A, B, C, D, E) __builtin_ia32_cmpph256_mask_round(A, B, 1, D, 8)
|
||||
#define __builtin_ia32_cmpps256_mask_round(A, B, C, D, E) __builtin_ia32_cmpps256_mask_round(A, B, 1, D, 8)
|
||||
#define __builtin_ia32_vcvtdq2ph256_mask_round(A, B, C, D) __builtin_ia32_vcvtdq2ph256_mask_round(A, B, C, 8)
|
||||
#define __builtin_ia32_cvtdq2ps256_mask_round(A, B, C, D) __builtin_ia32_cvtdq2ps256_mask_round(A, B, C, 8)
|
||||
#define __builtin_ia32_vcvtpd2ph256_mask_round(A, B, C, D) __builtin_ia32_vcvtpd2ph256_mask_round(A, B, C, 8)
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#define __builtin_ia32_cvtpd2ps256_mask_round(A, B, C, D) __builtin_ia32_cvtpd2ps256_mask_round(A, B, C, 8)
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#pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,fma,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,sha,xsavec,xsaves,clflushopt,clwb,mwaitx,clzero,pku,sgx,rdpid,gfni,vpclmulqdq,pconfig,wbnoinvd,enqcmd,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avxifma,avxvnniint8,avxneconvert,cmpccxadd,amx-fp16,prefetchi,raoint,amx-complex,avxvnniint16,sm3,sha512,sm4,avx10.2-512")
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Loading…
Add table
Reference in a new issue