RISC-V: Remove autovec-vls.md file and clean up VLS move modes[NFC]
We have largely supportted VLS modes. Only move patterns of VLS modes are different from VLS patterns. The rest of them are the same. We always extend the current VLA patterns with VLSmodes: VI --> V_VLSI VF --> V_VLSF It makes no sense to have a separate file holding a very few VLS patterns that can not be extended from the current VLA patterns. So remove autovec-vls.md gcc/ChangeLog: * config/riscv/vector.md (mov<mode>): New pattern. (*mov<mode>_mem_to_mem): Ditto. (*mov<mode>): Ditto. (@mov<VLS_AVL_REG:mode><P:mode>_lra): Ditto. (*mov<VLS_AVL_REG:mode><P:mode>_lra): Ditto. (*mov<mode>_vls): Ditto. (movmisalign<mode>): Ditto. (@vec_duplicate<mode>): Ditto. * config/riscv/autovec-vls.md: Removed.
This commit is contained in:
Juzhe-Zhong
Pan Li
parent
fafd2502c5
commit
4e679b9cea
2 changed files with 170 additions and 198 deletions
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@ -1,196 +0,0 @@
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;; Machine description for VLS of RVV auto-vectorization.
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;; Copyright (C) 2023 Free Software Foundation, Inc.
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;; Contributed by Juzhe Zhong (juzhe.zhong@rivai.ai), RiVAI Technologies Ltd.
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;; This file is part of GCC.
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;; GCC is free software; you can redistribute it and/or modify
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;; it under the terms of the GNU General Public License as published by
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;; the Free Software Foundation; either version 3, or (at your option)
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;; any later version.
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;; GCC is distributed in the hope that it will be useful,
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;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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;; GNU General Public License for more details.
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; <http://www.gnu.org/licenses/>.
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;; We define VLS modes as 'define_insn_and_split' with normal
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;; RTX_CODE operation, so we can gain benefits from Combine optimizations.
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;; -----------------------------------------------------------------
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;; ---- Moves Operations
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;; -----------------------------------------------------------------
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(define_expand "mov<mode>"
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[(set (match_operand:VLS_AVL_IMM 0 "reg_or_mem_operand")
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(match_operand:VLS_AVL_IMM 1 "general_operand"))]
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"TARGET_VECTOR"
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{
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if (riscv_vector::legitimize_move (operands[0], operands[1]))
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DONE;
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})
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(define_insn_and_split "*mov<mode>_mem_to_mem"
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[(set (match_operand:VLS_AVL_IMM 0 "memory_operand")
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(match_operand:VLS_AVL_IMM 1 "memory_operand"))]
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"TARGET_VECTOR && can_create_pseudo_p ()"
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"#"
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"&& 1"
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[(const_int 0)]
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{
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if (GET_MODE_BITSIZE (<MODE>mode).to_constant () <= MAX_BITS_PER_WORD)
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{
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/* Opitmize the following case:
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typedef int8_t v2qi __attribute__ ((vector_size (2)));
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v2qi v = *(v2qi*)in;
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*(v2qi*)out = v;
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We prefer scalar load/store instead of vle.v/vse.v when
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the VLS modes size is smaller scalar mode. */
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machine_mode mode;
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unsigned size = GET_MODE_BITSIZE (<MODE>mode).to_constant ();
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if (FLOAT_MODE_P (<MODE>mode))
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mode = mode_for_size (size, MODE_FLOAT, 0).require ();
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else
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mode = mode_for_size (size, MODE_INT, 0).require ();
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emit_move_insn (gen_lowpart (mode, operands[0]),
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gen_lowpart (mode, operands[1]));
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}
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else
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{
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operands[1] = force_reg (<MODE>mode, operands[1]);
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emit_move_insn (operands[0], operands[1]);
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}
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DONE;
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}
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[(set_attr "type" "vmov")]
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)
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(define_insn_and_split "*mov<mode>"
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[(set (match_operand:VLS_AVL_IMM 0 "reg_or_mem_operand" "=vr, m, vr")
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(match_operand:VLS_AVL_IMM 1 "reg_or_mem_operand" " m,vr, vr"))]
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"TARGET_VECTOR
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&& (register_operand (operands[0], <MODE>mode)
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|| register_operand (operands[1], <MODE>mode))"
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"@
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#
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#
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vmv%m1r.v\t%0,%1"
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"&& reload_completed
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&& (!register_operand (operands[0], <MODE>mode)
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|| !register_operand (operands[1], <MODE>mode))"
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[(const_int 0)]
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{
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bool ok_p = riscv_vector::legitimize_move (operands[0], operands[1]);
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gcc_assert (ok_p);
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DONE;
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}
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[(set_attr "type" "vmov")]
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)
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(define_expand "mov<mode>"
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[(set (match_operand:VLS_AVL_REG 0 "reg_or_mem_operand")
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(match_operand:VLS_AVL_REG 1 "general_operand"))]
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"TARGET_VECTOR"
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{
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bool ok_p = riscv_vector::legitimize_move (operands[0], operands[1]);
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gcc_assert (ok_p);
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DONE;
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})
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(define_expand "@mov<VLS_AVL_REG:mode><P:mode>_lra"
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[(parallel
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[(set (match_operand:VLS_AVL_REG 0 "reg_or_mem_operand")
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(match_operand:VLS_AVL_REG 1 "reg_or_mem_operand"))
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(clobber (match_scratch:P 2))])]
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"TARGET_VECTOR && (lra_in_progress || reload_completed)"
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{})
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(define_insn_and_split "*mov<VLS_AVL_REG:mode><P:mode>_lra"
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[(set (match_operand:VLS_AVL_REG 0 "reg_or_mem_operand" "=vr, m,vr")
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(match_operand:VLS_AVL_REG 1 "reg_or_mem_operand" " m,vr,vr"))
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(clobber (match_scratch:P 2 "=&r,&r,X"))]
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"TARGET_VECTOR && (lra_in_progress || reload_completed)
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&& (register_operand (operands[0], <VLS_AVL_REG:MODE>mode)
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|| register_operand (operands[1], <VLS_AVL_REG:MODE>mode))"
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"#"
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"&& reload_completed"
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[(const_int 0)]
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{
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if (REG_P (operands[0]) && REG_P (operands[1]))
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emit_insn (gen_rtx_SET (operands[0], operands[1]));
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else
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{
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emit_move_insn (operands[2], gen_int_mode (GET_MODE_NUNITS (<VLS_AVL_REG:MODE>mode),
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Pmode));
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unsigned insn_flags
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= GET_MODE_CLASS (<VLS_AVL_REG:MODE>mode) == MODE_VECTOR_BOOL
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? riscv_vector::UNARY_MASK_OP
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: riscv_vector::UNARY_OP;
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riscv_vector::emit_nonvlmax_insn (code_for_pred_mov (<VLS_AVL_REG:MODE>mode),
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insn_flags, operands, operands[2]);
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}
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DONE;
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}
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[(set_attr "type" "vmov")]
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)
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(define_insn "*mov<mode>_vls"
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[(set (match_operand:VLS 0 "register_operand" "=vr")
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(match_operand:VLS 1 "register_operand" " vr"))]
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"TARGET_VECTOR"
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"vmv%m1r.v\t%0,%1"
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[(set_attr "type" "vmov")
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(set_attr "mode" "<MODE>")])
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(define_insn "*mov<mode>_vls"
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[(set (match_operand:VLSB 0 "register_operand" "=vr")
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(match_operand:VLSB 1 "register_operand" " vr"))]
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"TARGET_VECTOR"
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"vmv1r.v\t%0,%1"
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[(set_attr "type" "vmov")
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(set_attr "mode" "<MODE>")])
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(define_expand "movmisalign<mode>"
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[(set (match_operand:VLS 0 "nonimmediate_operand")
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(match_operand:VLS 1 "general_operand"))]
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"TARGET_VECTOR"
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{
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/* To support misalign data movement, we should use
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minimum element alignment load/store. */
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unsigned int size = GET_MODE_SIZE (GET_MODE_INNER (<MODE>mode));
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poly_int64 nunits = GET_MODE_NUNITS (<MODE>mode) * size;
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machine_mode mode = riscv_vector::get_vector_mode (QImode, nunits).require ();
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operands[0] = gen_lowpart (mode, operands[0]);
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operands[1] = gen_lowpart (mode, operands[1]);
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if (MEM_P (operands[0]) && !register_operand (operands[1], mode))
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operands[1] = force_reg (mode, operands[1]);
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riscv_vector::emit_vlmax_insn (code_for_pred_mov (mode), riscv_vector::UNARY_OP, operands);
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DONE;
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}
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)
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;; -----------------------------------------------------------------
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;; ---- Duplicate Operations
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;; -----------------------------------------------------------------
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(define_insn_and_split "@vec_duplicate<mode>"
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[(set (match_operand:VLS 0 "register_operand")
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(vec_duplicate:VLS
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(match_operand:<VEL> 1 "reg_or_int_operand")))]
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"TARGET_VECTOR && can_create_pseudo_p ()"
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"#"
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"&& 1"
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[(const_int 0)]
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{
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riscv_vector::emit_vlmax_insn (code_for_pred_broadcast (<MODE>mode),
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riscv_vector::UNARY_OP, operands);
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DONE;
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}
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[(set_attr "type" "vector")]
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)
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@ -25,7 +25,6 @@
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;; - Intrinsics (https://github.com/riscv/rvv-intrinsic-doc)
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;; - Auto-vectorization (autovec.md)
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;; - Optimization (autovec-opt.md)
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;; - VLS patterns (autovec-vls.md)
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(include "vector-iterators.md")
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@ -1210,6 +1209,160 @@
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[(set_attr "type" "vmov,vlde,vste")
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(set_attr "mode" "<VT:MODE>")])
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;; -----------------------------------------------------------------
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;; ---- VLS Moves Operations
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;; -----------------------------------------------------------------
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(define_expand "mov<mode>"
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[(set (match_operand:VLS_AVL_IMM 0 "reg_or_mem_operand")
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(match_operand:VLS_AVL_IMM 1 "general_operand"))]
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"TARGET_VECTOR"
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{
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if (riscv_vector::legitimize_move (operands[0], operands[1]))
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DONE;
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})
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(define_insn_and_split "*mov<mode>_mem_to_mem"
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[(set (match_operand:VLS_AVL_IMM 0 "memory_operand")
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(match_operand:VLS_AVL_IMM 1 "memory_operand"))]
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"TARGET_VECTOR && can_create_pseudo_p ()"
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"#"
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"&& 1"
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[(const_int 0)]
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{
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if (GET_MODE_BITSIZE (<MODE>mode).to_constant () <= MAX_BITS_PER_WORD)
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{
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/* Opitmize the following case:
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typedef int8_t v2qi __attribute__ ((vector_size (2)));
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v2qi v = *(v2qi*)in;
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*(v2qi*)out = v;
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We prefer scalar load/store instead of vle.v/vse.v when
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the VLS modes size is smaller scalar mode. */
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machine_mode mode;
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unsigned size = GET_MODE_BITSIZE (<MODE>mode).to_constant ();
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if (FLOAT_MODE_P (<MODE>mode))
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mode = mode_for_size (size, MODE_FLOAT, 0).require ();
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else
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mode = mode_for_size (size, MODE_INT, 0).require ();
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emit_move_insn (gen_lowpart (mode, operands[0]),
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gen_lowpart (mode, operands[1]));
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}
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else
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{
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operands[1] = force_reg (<MODE>mode, operands[1]);
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emit_move_insn (operands[0], operands[1]);
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}
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DONE;
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}
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[(set_attr "type" "vmov")]
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)
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(define_insn_and_split "*mov<mode>"
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[(set (match_operand:VLS_AVL_IMM 0 "reg_or_mem_operand" "=vr, m, vr")
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(match_operand:VLS_AVL_IMM 1 "reg_or_mem_operand" " m,vr, vr"))]
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"TARGET_VECTOR
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&& (register_operand (operands[0], <MODE>mode)
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|| register_operand (operands[1], <MODE>mode))"
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"@
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#
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#
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vmv%m1r.v\t%0,%1"
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"&& reload_completed
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&& (!register_operand (operands[0], <MODE>mode)
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|| !register_operand (operands[1], <MODE>mode))"
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[(const_int 0)]
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{
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bool ok_p = riscv_vector::legitimize_move (operands[0], operands[1]);
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gcc_assert (ok_p);
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DONE;
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}
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[(set_attr "type" "vmov")]
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)
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(define_expand "mov<mode>"
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[(set (match_operand:VLS_AVL_REG 0 "reg_or_mem_operand")
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(match_operand:VLS_AVL_REG 1 "general_operand"))]
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"TARGET_VECTOR"
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{
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bool ok_p = riscv_vector::legitimize_move (operands[0], operands[1]);
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gcc_assert (ok_p);
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DONE;
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})
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(define_expand "@mov<VLS_AVL_REG:mode><P:mode>_lra"
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[(parallel
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[(set (match_operand:VLS_AVL_REG 0 "reg_or_mem_operand")
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(match_operand:VLS_AVL_REG 1 "reg_or_mem_operand"))
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(clobber (match_scratch:P 2))])]
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"TARGET_VECTOR && (lra_in_progress || reload_completed)"
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{})
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(define_insn_and_split "*mov<VLS_AVL_REG:mode><P:mode>_lra"
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[(set (match_operand:VLS_AVL_REG 0 "reg_or_mem_operand" "=vr, m,vr")
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(match_operand:VLS_AVL_REG 1 "reg_or_mem_operand" " m,vr,vr"))
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(clobber (match_scratch:P 2 "=&r,&r,X"))]
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"TARGET_VECTOR && (lra_in_progress || reload_completed)
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&& (register_operand (operands[0], <VLS_AVL_REG:MODE>mode)
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|| register_operand (operands[1], <VLS_AVL_REG:MODE>mode))"
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"#"
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"&& reload_completed"
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[(const_int 0)]
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{
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if (REG_P (operands[0]) && REG_P (operands[1]))
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emit_insn (gen_rtx_SET (operands[0], operands[1]));
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else
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{
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emit_move_insn (operands[2], gen_int_mode (GET_MODE_NUNITS (<VLS_AVL_REG:MODE>mode),
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Pmode));
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unsigned insn_flags
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= GET_MODE_CLASS (<VLS_AVL_REG:MODE>mode) == MODE_VECTOR_BOOL
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? riscv_vector::UNARY_MASK_OP
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: riscv_vector::UNARY_OP;
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riscv_vector::emit_nonvlmax_insn (code_for_pred_mov (<VLS_AVL_REG:MODE>mode),
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insn_flags, operands, operands[2]);
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}
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DONE;
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}
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[(set_attr "type" "vmov")]
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)
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(define_insn "*mov<mode>_vls"
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[(set (match_operand:VLS 0 "register_operand" "=vr")
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(match_operand:VLS 1 "register_operand" " vr"))]
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"TARGET_VECTOR"
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"vmv%m1r.v\t%0,%1"
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[(set_attr "type" "vmov")
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(set_attr "mode" "<MODE>")])
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(define_insn "*mov<mode>_vls"
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[(set (match_operand:VLSB 0 "register_operand" "=vr")
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(match_operand:VLSB 1 "register_operand" " vr"))]
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"TARGET_VECTOR"
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"vmv1r.v\t%0,%1"
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[(set_attr "type" "vmov")
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(set_attr "mode" "<MODE>")])
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(define_expand "movmisalign<mode>"
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[(set (match_operand:VLS 0 "nonimmediate_operand")
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(match_operand:VLS 1 "general_operand"))]
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"TARGET_VECTOR"
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{
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/* To support misalign data movement, we should use
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minimum element alignment load/store. */
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unsigned int size = GET_MODE_SIZE (GET_MODE_INNER (<MODE>mode));
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poly_int64 nunits = GET_MODE_NUNITS (<MODE>mode) * size;
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machine_mode mode = riscv_vector::get_vector_mode (QImode, nunits).require ();
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operands[0] = gen_lowpart (mode, operands[0]);
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operands[1] = gen_lowpart (mode, operands[1]);
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if (MEM_P (operands[0]) && !register_operand (operands[1], mode))
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operands[1] = force_reg (mode, operands[1]);
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riscv_vector::emit_vlmax_insn (code_for_pred_mov (mode), riscv_vector::UNARY_OP, operands);
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DONE;
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}
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)
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;; -----------------------------------------------------------------
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;; ---- Duplicate Operations
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;; -----------------------------------------------------------------
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@ -1230,6 +1383,22 @@
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}
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)
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(define_insn_and_split "@vec_duplicate<mode>"
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[(set (match_operand:VLS 0 "register_operand")
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(vec_duplicate:VLS
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(match_operand:<VEL> 1 "reg_or_int_operand")))]
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"TARGET_VECTOR && can_create_pseudo_p ()"
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"#"
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"&& 1"
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[(const_int 0)]
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{
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riscv_vector::emit_vlmax_insn (code_for_pred_broadcast (<MODE>mode),
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riscv_vector::UNARY_OP, operands);
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DONE;
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}
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[(set_attr "type" "vector")]
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)
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;; -----------------------------------------------------------------
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;; ---- 6. Configuration-Setting Instructions
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;; -----------------------------------------------------------------
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@ -8540,4 +8709,3 @@
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(include "autovec.md")
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(include "autovec-opt.md")
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(include "autovec-vls.md")
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue