RISC-V: Support VLS modes reduction[PR111153]
This patch supports VLS reduction vectorization.
It can optimize the current reduction vectorization codegen with current COST model.
TYPE __attribute__ ((noinline, noclone)) \
reduc_plus_##TYPE (TYPE * __restrict a, int n) \
{ \
TYPE r = 0; \
for (int i = 0; i < n; ++i) \
r += a[i]; \
return r; \
}
T (int32_t) \
TEST_PLUS (DEF_REDUC_PLUS)
Before this patch:
vle32.v v2,0(a5)
addi a5,a5,16
vadd.vv v1,v1,v2
bne a5,a4,.L4
lui a4,%hi(.LC0)
lui a5,%hi(.LC1)
addi a4,a4,%lo(.LC0)
vlm.v v0,0(a4)
addi a5,a5,%lo(.LC1)
andi a1,a1,-4
vmv1r.v v2,v3
vlm.v v4,0(a5)
vcompress.vm v2,v1,v0
vmv1r.v v0,v4
vadd.vv v1,v2,v1
vcompress.vm v3,v1,v0
vadd.vv v3,v3,v1
vmv.x.s a0,v3
sext.w a0,a0
beq a3,a1,.L12
After this patch:
vle32.v v2,0(a5)
addi a5,a5,16
vadd.vv v1,v1,v2
bne a5,a4,.L4
li a5,0
andi a1,a1,-4
vmv.s.x v2,a5
vredsum.vs v1,v1,v2
vmv.x.s a0,v1
beq a3,a1,.L12
PR target/111153
gcc/ChangeLog:
* config/riscv/autovec.md: Add VLS modes.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vls/def.h: Add VLS mode reduction case.
* gcc.target/riscv/rvv/autovec/vls/reduc-1.c: New test.
* gcc.target/riscv/rvv/autovec/vls/reduc-10.c: New test.
* gcc.target/riscv/rvv/autovec/vls/reduc-11.c: New test.
* gcc.target/riscv/rvv/autovec/vls/reduc-12.c: New test.
* gcc.target/riscv/rvv/autovec/vls/reduc-13.c: New test.
* gcc.target/riscv/rvv/autovec/vls/reduc-14.c: New test.
* gcc.target/riscv/rvv/autovec/vls/reduc-15.c: New test.
* gcc.target/riscv/rvv/autovec/vls/reduc-16.c: New test.
* gcc.target/riscv/rvv/autovec/vls/reduc-17.c: New test.
* gcc.target/riscv/rvv/autovec/vls/reduc-18.c: New test.
* gcc.target/riscv/rvv/autovec/vls/reduc-19.c: New test.
* gcc.target/riscv/rvv/autovec/vls/reduc-2.c: New test.
* gcc.target/riscv/rvv/autovec/vls/reduc-20.c: New test.
* gcc.target/riscv/rvv/autovec/vls/reduc-21.c: New test.
* gcc.target/riscv/rvv/autovec/vls/reduc-3.c: New test.
* gcc.target/riscv/rvv/autovec/vls/reduc-4.c: New test.
* gcc.target/riscv/rvv/autovec/vls/reduc-5.c: New test.
* gcc.target/riscv/rvv/autovec/vls/reduc-6.c: New test.
* gcc.target/riscv/rvv/autovec/vls/reduc-7.c: New test.
* gcc.target/riscv/rvv/autovec/vls/reduc-8.c: New test.
* gcc.target/riscv/rvv/autovec/vls/reduc-9.c: New test.
This commit is contained in:
Juzhe-Zhong
Pan Li
parent
93996cfb30
commit
fafd2502c5
23 changed files with 825 additions and 1 deletions
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@ -2241,7 +2241,7 @@
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(define_insn_and_split "fold_left_plus_<mode>"
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[(set (match_operand:<VEL> 0 "register_operand")
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(unspec:<VEL> [
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(match_operand:VF 2 "register_operand")
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(match_operand:V_VLSF 2 "register_operand")
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(match_operand:<VEL> 1 "register_operand")
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] UNSPEC_REDUC_SUM_ORDERED))]
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"TARGET_VECTOR && can_create_pseudo_p ()"
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@ -266,3 +266,33 @@ typedef double v512df __attribute__ ((vector_size (4096)));
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for (int i = 0; i < NUM; ++i) \
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a[i] = b[i] * CALL (1.0, c[i]); \
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}
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#define DEF_REDUC_PLUS(TYPE, NUM) \
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TYPE __attribute__ ((noinline, noclone)) \
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reduc_plus_##TYPE##NUM (TYPE *__restrict a) \
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{ \
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TYPE r = 0; \
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for (int i = 0; i < NUM; ++i) \
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r += a[i]; \
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return r; \
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}
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#define DEF_REDUC_MAXMIN(TYPE, NAME, CMP_OP, NUM) \
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TYPE __attribute__ ((noinline, noclone)) \
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reduc_##NAME##_##TYPE##_##NUM (TYPE *a) \
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{ \
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TYPE r = 13; \
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for (int i = 0; i < NUM; ++i) \
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r = a[i] CMP_OP r ? a[i] : r; \
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return r; \
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}
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#define DEF_REDUC_BITWISE(TYPE, NAME, BIT_OP, NUM) \
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TYPE __attribute__ ((noinline, noclone)) \
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reduc_##NAME##_##TYPE##_##NUM (TYPE *a) \
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{ \
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TYPE r = 13; \
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for (int i = 0; i < NUM; ++i) \
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r BIT_OP a[i]; \
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return r; \
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}
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31
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-1.c
Normal file
31
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-1.c
Normal file
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@ -0,0 +1,31 @@
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/* { dg-do compile } */
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/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
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#include "def.h"
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DEF_REDUC_PLUS (int8_t, 4)
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DEF_REDUC_PLUS (int8_t, 8)
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DEF_REDUC_PLUS (int8_t, 16)
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DEF_REDUC_PLUS (int8_t, 32)
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DEF_REDUC_PLUS (int8_t, 64)
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DEF_REDUC_PLUS (int8_t, 128)
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DEF_REDUC_PLUS (int8_t, 256)
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DEF_REDUC_PLUS (int8_t, 512)
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DEF_REDUC_PLUS (int8_t, 1024)
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DEF_REDUC_PLUS (int8_t, 2048)
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DEF_REDUC_PLUS (int8_t, 4096)
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DEF_REDUC_PLUS (uint8_t, 4)
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DEF_REDUC_PLUS (uint8_t, 8)
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DEF_REDUC_PLUS (uint8_t, 16)
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DEF_REDUC_PLUS (uint8_t, 32)
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DEF_REDUC_PLUS (uint8_t, 64)
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DEF_REDUC_PLUS (uint8_t, 128)
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DEF_REDUC_PLUS (uint8_t, 256)
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DEF_REDUC_PLUS (uint8_t, 512)
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DEF_REDUC_PLUS (uint8_t, 1024)
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DEF_REDUC_PLUS (uint8_t, 2048)
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DEF_REDUC_PLUS (uint8_t, 4096)
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/* { dg-final { scan-assembler-times {vredsum\.vs} 22 } } */
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/* { dg-final { scan-assembler-not {csrr} } } */
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50
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-10.c
Normal file
50
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-10.c
Normal file
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@ -0,0 +1,50 @@
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/* { dg-do compile } */
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/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
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#include "def.h"
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DEF_REDUC_MAXMIN (int32_t, max, >, 4)
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DEF_REDUC_MAXMIN (int32_t, max, >, 8)
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DEF_REDUC_MAXMIN (int32_t, max, >, 16)
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DEF_REDUC_MAXMIN (int32_t, max, >, 32)
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DEF_REDUC_MAXMIN (int32_t, max, >, 64)
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DEF_REDUC_MAXMIN (int32_t, max, >, 128)
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DEF_REDUC_MAXMIN (int32_t, max, >, 256)
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DEF_REDUC_MAXMIN (int32_t, max, >, 512)
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DEF_REDUC_MAXMIN (int32_t, max, >, 1024)
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DEF_REDUC_MAXMIN (uint32_t, max, >, 4)
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DEF_REDUC_MAXMIN (uint32_t, max, >, 8)
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DEF_REDUC_MAXMIN (uint32_t, max, >, 16)
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DEF_REDUC_MAXMIN (uint32_t, max, >, 32)
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DEF_REDUC_MAXMIN (uint32_t, max, >, 64)
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DEF_REDUC_MAXMIN (uint32_t, max, >, 128)
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DEF_REDUC_MAXMIN (uint32_t, max, >, 256)
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DEF_REDUC_MAXMIN (uint32_t, max, >, 512)
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DEF_REDUC_MAXMIN (uint32_t, max, >, 1024)
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DEF_REDUC_MAXMIN (int32_t, min, <, 4)
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DEF_REDUC_MAXMIN (int32_t, min, <, 8)
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DEF_REDUC_MAXMIN (int32_t, min, <, 16)
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DEF_REDUC_MAXMIN (int32_t, min, <, 32)
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DEF_REDUC_MAXMIN (int32_t, min, <, 64)
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DEF_REDUC_MAXMIN (int32_t, min, <, 128)
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DEF_REDUC_MAXMIN (int32_t, min, <, 256)
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DEF_REDUC_MAXMIN (int32_t, min, <, 512)
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DEF_REDUC_MAXMIN (int32_t, min, <, 1024)
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DEF_REDUC_MAXMIN (uint32_t, min, <, 4)
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DEF_REDUC_MAXMIN (uint32_t, min, <, 8)
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DEF_REDUC_MAXMIN (uint32_t, min, <, 16)
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DEF_REDUC_MAXMIN (uint32_t, min, <, 32)
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DEF_REDUC_MAXMIN (uint32_t, min, <, 64)
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DEF_REDUC_MAXMIN (uint32_t, min, <, 128)
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DEF_REDUC_MAXMIN (uint32_t, min, <, 256)
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DEF_REDUC_MAXMIN (uint32_t, min, <, 512)
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DEF_REDUC_MAXMIN (uint32_t, min, <, 1024)
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/* { dg-final { scan-assembler-times {vredmax\.vs} 9 } } */
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/* { dg-final { scan-assembler-times {vredmaxu\.vs} 9 } } */
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/* { dg-final { scan-assembler-times {vredmin\.vs} 9 } } */
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/* { dg-final { scan-assembler-times {vredminu\.vs} 9 } } */
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/* { dg-final { scan-assembler-not {csrr} } } */
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46
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-11.c
Normal file
46
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-11.c
Normal file
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@ -0,0 +1,46 @@
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/* { dg-do compile } */
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/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
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#include "def.h"
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DEF_REDUC_MAXMIN (int64_t, max, >, 4)
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DEF_REDUC_MAXMIN (int64_t, max, >, 8)
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DEF_REDUC_MAXMIN (int64_t, max, >, 16)
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DEF_REDUC_MAXMIN (int64_t, max, >, 32)
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DEF_REDUC_MAXMIN (int64_t, max, >, 64)
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DEF_REDUC_MAXMIN (int64_t, max, >, 128)
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DEF_REDUC_MAXMIN (int64_t, max, >, 256)
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DEF_REDUC_MAXMIN (int64_t, max, >, 512)
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DEF_REDUC_MAXMIN (uint64_t, max, >, 4)
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DEF_REDUC_MAXMIN (uint64_t, max, >, 8)
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DEF_REDUC_MAXMIN (uint64_t, max, >, 16)
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DEF_REDUC_MAXMIN (uint64_t, max, >, 32)
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DEF_REDUC_MAXMIN (uint64_t, max, >, 64)
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DEF_REDUC_MAXMIN (uint64_t, max, >, 128)
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DEF_REDUC_MAXMIN (uint64_t, max, >, 256)
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DEF_REDUC_MAXMIN (uint64_t, max, >, 512)
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DEF_REDUC_MAXMIN (int64_t, min, <, 4)
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DEF_REDUC_MAXMIN (int64_t, min, <, 8)
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DEF_REDUC_MAXMIN (int64_t, min, <, 16)
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DEF_REDUC_MAXMIN (int64_t, min, <, 32)
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DEF_REDUC_MAXMIN (int64_t, min, <, 64)
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DEF_REDUC_MAXMIN (int64_t, min, <, 128)
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DEF_REDUC_MAXMIN (int64_t, min, <, 256)
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DEF_REDUC_MAXMIN (int64_t, min, <, 512)
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DEF_REDUC_MAXMIN (uint64_t, min, <, 4)
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DEF_REDUC_MAXMIN (uint64_t, min, <, 8)
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DEF_REDUC_MAXMIN (uint64_t, min, <, 16)
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DEF_REDUC_MAXMIN (uint64_t, min, <, 32)
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DEF_REDUC_MAXMIN (uint64_t, min, <, 64)
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DEF_REDUC_MAXMIN (uint64_t, min, <, 128)
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DEF_REDUC_MAXMIN (uint64_t, min, <, 256)
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DEF_REDUC_MAXMIN (uint64_t, min, <, 512)
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/* { dg-final { scan-assembler-times {vredmax\.vs} 8 } } */
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/* { dg-final { scan-assembler-times {vredmaxu\.vs} 8 } } */
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/* { dg-final { scan-assembler-times {vredmin\.vs} 8 } } */
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/* { dg-final { scan-assembler-times {vredminu\.vs} 8 } } */
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/* { dg-final { scan-assembler-not {csrr} } } */
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30
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-12.c
Normal file
30
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-12.c
Normal file
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@ -0,0 +1,30 @@
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/* { dg-do compile } */
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/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math" } */
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#include "def.h"
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DEF_REDUC_MAXMIN (_Float16, max, >, 4)
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DEF_REDUC_MAXMIN (_Float16, max, >, 8)
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DEF_REDUC_MAXMIN (_Float16, max, >, 16)
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DEF_REDUC_MAXMIN (_Float16, max, >, 32)
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DEF_REDUC_MAXMIN (_Float16, max, >, 64)
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DEF_REDUC_MAXMIN (_Float16, max, >, 128)
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DEF_REDUC_MAXMIN (_Float16, max, >, 256)
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DEF_REDUC_MAXMIN (_Float16, max, >, 512)
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DEF_REDUC_MAXMIN (_Float16, max, >, 1024)
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DEF_REDUC_MAXMIN (_Float16, max, >, 2048)
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DEF_REDUC_MAXMIN (_Float16, min, <, 4)
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DEF_REDUC_MAXMIN (_Float16, min, <, 8)
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DEF_REDUC_MAXMIN (_Float16, min, <, 16)
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DEF_REDUC_MAXMIN (_Float16, min, <, 32)
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DEF_REDUC_MAXMIN (_Float16, min, <, 64)
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DEF_REDUC_MAXMIN (_Float16, min, <, 128)
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DEF_REDUC_MAXMIN (_Float16, min, <, 256)
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DEF_REDUC_MAXMIN (_Float16, min, <, 512)
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DEF_REDUC_MAXMIN (_Float16, min, <, 1024)
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DEF_REDUC_MAXMIN (_Float16, min, <, 2048)
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/* { dg-final { scan-assembler-times {vfredmax\.vs} 10 } } */
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/* { dg-final { scan-assembler-times {vfredmin\.vs} 10 } } */
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/* { dg-final { scan-assembler-not {csrr} } } */
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28
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-13.c
Normal file
28
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-13.c
Normal file
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@ -0,0 +1,28 @@
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/* { dg-do compile } */
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/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math" } */
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#include "def.h"
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DEF_REDUC_MAXMIN (float, max, >, 4)
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DEF_REDUC_MAXMIN (float, max, >, 8)
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DEF_REDUC_MAXMIN (float, max, >, 16)
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DEF_REDUC_MAXMIN (float, max, >, 32)
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DEF_REDUC_MAXMIN (float, max, >, 64)
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DEF_REDUC_MAXMIN (float, max, >, 128)
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DEF_REDUC_MAXMIN (float, max, >, 256)
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DEF_REDUC_MAXMIN (float, max, >, 512)
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DEF_REDUC_MAXMIN (float, max, >, 1024)
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DEF_REDUC_MAXMIN (float, min, <, 4)
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DEF_REDUC_MAXMIN (float, min, <, 8)
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DEF_REDUC_MAXMIN (float, min, <, 16)
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DEF_REDUC_MAXMIN (float, min, <, 32)
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DEF_REDUC_MAXMIN (float, min, <, 64)
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DEF_REDUC_MAXMIN (float, min, <, 128)
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DEF_REDUC_MAXMIN (float, min, <, 256)
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DEF_REDUC_MAXMIN (float, min, <, 512)
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DEF_REDUC_MAXMIN (float, min, <, 1024)
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/* { dg-final { scan-assembler-times {vfredmax\.vs} 9 } } */
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/* { dg-final { scan-assembler-times {vfredmin\.vs} 9 } } */
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/* { dg-final { scan-assembler-not {csrr} } } */
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26
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-14.c
Normal file
26
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-14.c
Normal file
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@ -0,0 +1,26 @@
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/* { dg-do compile } */
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/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math" } */
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#include "def.h"
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DEF_REDUC_MAXMIN (double, max, >, 4)
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DEF_REDUC_MAXMIN (double, max, >, 8)
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DEF_REDUC_MAXMIN (double, max, >, 16)
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DEF_REDUC_MAXMIN (double, max, >, 32)
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DEF_REDUC_MAXMIN (double, max, >, 64)
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DEF_REDUC_MAXMIN (double, max, >, 128)
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DEF_REDUC_MAXMIN (double, max, >, 256)
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DEF_REDUC_MAXMIN (double, max, >, 512)
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DEF_REDUC_MAXMIN (double, min, <, 4)
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DEF_REDUC_MAXMIN (double, min, <, 8)
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DEF_REDUC_MAXMIN (double, min, <, 16)
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DEF_REDUC_MAXMIN (double, min, <, 32)
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DEF_REDUC_MAXMIN (double, min, <, 64)
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DEF_REDUC_MAXMIN (double, min, <, 128)
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DEF_REDUC_MAXMIN (double, min, <, 256)
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DEF_REDUC_MAXMIN (double, min, <, 512)
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/* { dg-final { scan-assembler-times {vfredmax\.vs} 8 } } */
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/* { dg-final { scan-assembler-times {vfredmin\.vs} 8 } } */
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/* { dg-final { scan-assembler-not {csrr} } } */
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81
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-15.c
Normal file
81
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-15.c
Normal file
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@ -0,0 +1,81 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
|
||||
|
||||
#include "def.h"
|
||||
|
||||
DEF_REDUC_BITWISE (int8_t, and, &=, 4)
|
||||
DEF_REDUC_BITWISE (int8_t, and, &=, 8)
|
||||
DEF_REDUC_BITWISE (int8_t, and, &=, 16)
|
||||
DEF_REDUC_BITWISE (int8_t, and, &=, 32)
|
||||
DEF_REDUC_BITWISE (int8_t, and, &=, 64)
|
||||
DEF_REDUC_BITWISE (int8_t, and, &=, 128)
|
||||
DEF_REDUC_BITWISE (int8_t, and, &=, 256)
|
||||
DEF_REDUC_BITWISE (int8_t, and, &=, 512)
|
||||
DEF_REDUC_BITWISE (int8_t, and, &=, 1024)
|
||||
DEF_REDUC_BITWISE (int8_t, and, &=, 2048)
|
||||
DEF_REDUC_BITWISE (int8_t, and, &=, 4096)
|
||||
|
||||
DEF_REDUC_BITWISE (uint8_t, and, &=, 4)
|
||||
DEF_REDUC_BITWISE (uint8_t, and, &=, 8)
|
||||
DEF_REDUC_BITWISE (uint8_t, and, &=, 16)
|
||||
DEF_REDUC_BITWISE (uint8_t, and, &=, 32)
|
||||
DEF_REDUC_BITWISE (uint8_t, and, &=, 64)
|
||||
DEF_REDUC_BITWISE (uint8_t, and, &=, 128)
|
||||
DEF_REDUC_BITWISE (uint8_t, and, &=, 256)
|
||||
DEF_REDUC_BITWISE (uint8_t, and, &=, 512)
|
||||
DEF_REDUC_BITWISE (uint8_t, and, &=, 1024)
|
||||
DEF_REDUC_BITWISE (uint8_t, and, &=, 2048)
|
||||
DEF_REDUC_BITWISE (uint8_t, and, &=, 4096)
|
||||
|
||||
DEF_REDUC_BITWISE (int8_t, ior, |=, 4)
|
||||
DEF_REDUC_BITWISE (int8_t, ior, |=, 8)
|
||||
DEF_REDUC_BITWISE (int8_t, ior, |=, 16)
|
||||
DEF_REDUC_BITWISE (int8_t, ior, |=, 32)
|
||||
DEF_REDUC_BITWISE (int8_t, ior, |=, 64)
|
||||
DEF_REDUC_BITWISE (int8_t, ior, |=, 128)
|
||||
DEF_REDUC_BITWISE (int8_t, ior, |=, 256)
|
||||
DEF_REDUC_BITWISE (int8_t, ior, |=, 512)
|
||||
DEF_REDUC_BITWISE (int8_t, ior, |=, 1024)
|
||||
DEF_REDUC_BITWISE (int8_t, ior, |=, 2048)
|
||||
DEF_REDUC_BITWISE (int8_t, ior, |=, 4096)
|
||||
|
||||
DEF_REDUC_BITWISE (uint8_t, ior, |=, 4)
|
||||
DEF_REDUC_BITWISE (uint8_t, ior, |=, 8)
|
||||
DEF_REDUC_BITWISE (uint8_t, ior, |=, 16)
|
||||
DEF_REDUC_BITWISE (uint8_t, ior, |=, 32)
|
||||
DEF_REDUC_BITWISE (uint8_t, ior, |=, 64)
|
||||
DEF_REDUC_BITWISE (uint8_t, ior, |=, 128)
|
||||
DEF_REDUC_BITWISE (uint8_t, ior, |=, 256)
|
||||
DEF_REDUC_BITWISE (uint8_t, ior, |=, 512)
|
||||
DEF_REDUC_BITWISE (uint8_t, ior, |=, 1024)
|
||||
DEF_REDUC_BITWISE (uint8_t, ior, |=, 2048)
|
||||
DEF_REDUC_BITWISE (uint8_t, ior, |=, 4096)
|
||||
|
||||
DEF_REDUC_BITWISE (int8_t, xor, ^=, 4)
|
||||
DEF_REDUC_BITWISE (int8_t, xor, ^=, 8)
|
||||
DEF_REDUC_BITWISE (int8_t, xor, ^=, 16)
|
||||
DEF_REDUC_BITWISE (int8_t, xor, ^=, 32)
|
||||
DEF_REDUC_BITWISE (int8_t, xor, ^=, 64)
|
||||
DEF_REDUC_BITWISE (int8_t, xor, ^=, 128)
|
||||
DEF_REDUC_BITWISE (int8_t, xor, ^=, 256)
|
||||
DEF_REDUC_BITWISE (int8_t, xor, ^=, 512)
|
||||
DEF_REDUC_BITWISE (int8_t, xor, ^=, 1024)
|
||||
DEF_REDUC_BITWISE (int8_t, xor, ^=, 2048)
|
||||
DEF_REDUC_BITWISE (int8_t, xor, ^=, 4096)
|
||||
|
||||
DEF_REDUC_BITWISE (uint8_t, xor, ^=, 4)
|
||||
DEF_REDUC_BITWISE (uint8_t, xor, ^=, 8)
|
||||
DEF_REDUC_BITWISE (uint8_t, xor, ^=, 16)
|
||||
DEF_REDUC_BITWISE (uint8_t, xor, ^=, 32)
|
||||
DEF_REDUC_BITWISE (uint8_t, xor, ^=, 64)
|
||||
DEF_REDUC_BITWISE (uint8_t, xor, ^=, 128)
|
||||
DEF_REDUC_BITWISE (uint8_t, xor, ^=, 256)
|
||||
DEF_REDUC_BITWISE (uint8_t, xor, ^=, 512)
|
||||
DEF_REDUC_BITWISE (uint8_t, xor, ^=, 1024)
|
||||
DEF_REDUC_BITWISE (uint8_t, xor, ^=, 2048)
|
||||
DEF_REDUC_BITWISE (uint8_t, xor, ^=, 4096)
|
||||
|
||||
/* { dg-final { scan-assembler-times {vredand\.vs} 22 } } */
|
||||
/* { dg-final { scan-assembler-times {vredor\.vs} 22 } } */
|
||||
/* { dg-final { scan-assembler-times {vredxor\.vs} 22 } } */
|
||||
/* { dg-final { scan-assembler-not {csrr} } } */
|
||||
75
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-16.c
Normal file
75
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-16.c
Normal file
|
|
@ -0,0 +1,75 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
|
||||
|
||||
#include "def.h"
|
||||
|
||||
DEF_REDUC_BITWISE (int16_t, and, &=, 4)
|
||||
DEF_REDUC_BITWISE (int16_t, and, &=, 8)
|
||||
DEF_REDUC_BITWISE (int16_t, and, &=, 16)
|
||||
DEF_REDUC_BITWISE (int16_t, and, &=, 32)
|
||||
DEF_REDUC_BITWISE (int16_t, and, &=, 64)
|
||||
DEF_REDUC_BITWISE (int16_t, and, &=, 128)
|
||||
DEF_REDUC_BITWISE (int16_t, and, &=, 256)
|
||||
DEF_REDUC_BITWISE (int16_t, and, &=, 512)
|
||||
DEF_REDUC_BITWISE (int16_t, and, &=, 1024)
|
||||
DEF_REDUC_BITWISE (int16_t, and, &=, 2048)
|
||||
|
||||
DEF_REDUC_BITWISE (uint16_t, and, &=, 4)
|
||||
DEF_REDUC_BITWISE (uint16_t, and, &=, 8)
|
||||
DEF_REDUC_BITWISE (uint16_t, and, &=, 16)
|
||||
DEF_REDUC_BITWISE (uint16_t, and, &=, 32)
|
||||
DEF_REDUC_BITWISE (uint16_t, and, &=, 64)
|
||||
DEF_REDUC_BITWISE (uint16_t, and, &=, 128)
|
||||
DEF_REDUC_BITWISE (uint16_t, and, &=, 256)
|
||||
DEF_REDUC_BITWISE (uint16_t, and, &=, 512)
|
||||
DEF_REDUC_BITWISE (uint16_t, and, &=, 1024)
|
||||
DEF_REDUC_BITWISE (uint16_t, and, &=, 2048)
|
||||
|
||||
DEF_REDUC_BITWISE (int16_t, ior, |=, 4)
|
||||
DEF_REDUC_BITWISE (int16_t, ior, |=, 8)
|
||||
DEF_REDUC_BITWISE (int16_t, ior, |=, 16)
|
||||
DEF_REDUC_BITWISE (int16_t, ior, |=, 32)
|
||||
DEF_REDUC_BITWISE (int16_t, ior, |=, 64)
|
||||
DEF_REDUC_BITWISE (int16_t, ior, |=, 128)
|
||||
DEF_REDUC_BITWISE (int16_t, ior, |=, 256)
|
||||
DEF_REDUC_BITWISE (int16_t, ior, |=, 512)
|
||||
DEF_REDUC_BITWISE (int16_t, ior, |=, 1024)
|
||||
DEF_REDUC_BITWISE (int16_t, ior, |=, 2048)
|
||||
|
||||
DEF_REDUC_BITWISE (uint16_t, ior, |=, 4)
|
||||
DEF_REDUC_BITWISE (uint16_t, ior, |=, 8)
|
||||
DEF_REDUC_BITWISE (uint16_t, ior, |=, 16)
|
||||
DEF_REDUC_BITWISE (uint16_t, ior, |=, 32)
|
||||
DEF_REDUC_BITWISE (uint16_t, ior, |=, 64)
|
||||
DEF_REDUC_BITWISE (uint16_t, ior, |=, 128)
|
||||
DEF_REDUC_BITWISE (uint16_t, ior, |=, 256)
|
||||
DEF_REDUC_BITWISE (uint16_t, ior, |=, 512)
|
||||
DEF_REDUC_BITWISE (uint16_t, ior, |=, 1024)
|
||||
DEF_REDUC_BITWISE (uint16_t, ior, |=, 2048)
|
||||
|
||||
DEF_REDUC_BITWISE (int16_t, xor, ^=, 4)
|
||||
DEF_REDUC_BITWISE (int16_t, xor, ^=, 8)
|
||||
DEF_REDUC_BITWISE (int16_t, xor, ^=, 16)
|
||||
DEF_REDUC_BITWISE (int16_t, xor, ^=, 32)
|
||||
DEF_REDUC_BITWISE (int16_t, xor, ^=, 64)
|
||||
DEF_REDUC_BITWISE (int16_t, xor, ^=, 128)
|
||||
DEF_REDUC_BITWISE (int16_t, xor, ^=, 256)
|
||||
DEF_REDUC_BITWISE (int16_t, xor, ^=, 512)
|
||||
DEF_REDUC_BITWISE (int16_t, xor, ^=, 1024)
|
||||
DEF_REDUC_BITWISE (int16_t, xor, ^=, 2048)
|
||||
|
||||
DEF_REDUC_BITWISE (uint16_t, xor, ^=, 4)
|
||||
DEF_REDUC_BITWISE (uint16_t, xor, ^=, 8)
|
||||
DEF_REDUC_BITWISE (uint16_t, xor, ^=, 16)
|
||||
DEF_REDUC_BITWISE (uint16_t, xor, ^=, 32)
|
||||
DEF_REDUC_BITWISE (uint16_t, xor, ^=, 64)
|
||||
DEF_REDUC_BITWISE (uint16_t, xor, ^=, 128)
|
||||
DEF_REDUC_BITWISE (uint16_t, xor, ^=, 256)
|
||||
DEF_REDUC_BITWISE (uint16_t, xor, ^=, 512)
|
||||
DEF_REDUC_BITWISE (uint16_t, xor, ^=, 1024)
|
||||
DEF_REDUC_BITWISE (uint16_t, xor, ^=, 2048)
|
||||
|
||||
/* { dg-final { scan-assembler-times {vredand\.vs} 20 } } */
|
||||
/* { dg-final { scan-assembler-times {vredor\.vs} 20 } } */
|
||||
/* { dg-final { scan-assembler-times {vredxor\.vs} 20 } } */
|
||||
/* { dg-final { scan-assembler-not {csrr} } } */
|
||||
69
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-17.c
Normal file
69
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-17.c
Normal file
|
|
@ -0,0 +1,69 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
|
||||
|
||||
#include "def.h"
|
||||
|
||||
DEF_REDUC_BITWISE (int32_t, and, &=, 4)
|
||||
DEF_REDUC_BITWISE (int32_t, and, &=, 8)
|
||||
DEF_REDUC_BITWISE (int32_t, and, &=, 16)
|
||||
DEF_REDUC_BITWISE (int32_t, and, &=, 32)
|
||||
DEF_REDUC_BITWISE (int32_t, and, &=, 64)
|
||||
DEF_REDUC_BITWISE (int32_t, and, &=, 128)
|
||||
DEF_REDUC_BITWISE (int32_t, and, &=, 256)
|
||||
DEF_REDUC_BITWISE (int32_t, and, &=, 512)
|
||||
DEF_REDUC_BITWISE (int32_t, and, &=, 1024)
|
||||
|
||||
DEF_REDUC_BITWISE (uint32_t, and, &=, 4)
|
||||
DEF_REDUC_BITWISE (uint32_t, and, &=, 8)
|
||||
DEF_REDUC_BITWISE (uint32_t, and, &=, 16)
|
||||
DEF_REDUC_BITWISE (uint32_t, and, &=, 32)
|
||||
DEF_REDUC_BITWISE (uint32_t, and, &=, 64)
|
||||
DEF_REDUC_BITWISE (uint32_t, and, &=, 128)
|
||||
DEF_REDUC_BITWISE (uint32_t, and, &=, 256)
|
||||
DEF_REDUC_BITWISE (uint32_t, and, &=, 512)
|
||||
DEF_REDUC_BITWISE (uint32_t, and, &=, 1024)
|
||||
|
||||
DEF_REDUC_BITWISE (int32_t, ior, |=, 4)
|
||||
DEF_REDUC_BITWISE (int32_t, ior, |=, 8)
|
||||
DEF_REDUC_BITWISE (int32_t, ior, |=, 16)
|
||||
DEF_REDUC_BITWISE (int32_t, ior, |=, 32)
|
||||
DEF_REDUC_BITWISE (int32_t, ior, |=, 64)
|
||||
DEF_REDUC_BITWISE (int32_t, ior, |=, 128)
|
||||
DEF_REDUC_BITWISE (int32_t, ior, |=, 256)
|
||||
DEF_REDUC_BITWISE (int32_t, ior, |=, 512)
|
||||
DEF_REDUC_BITWISE (int32_t, ior, |=, 1024)
|
||||
|
||||
DEF_REDUC_BITWISE (uint32_t, ior, |=, 4)
|
||||
DEF_REDUC_BITWISE (uint32_t, ior, |=, 8)
|
||||
DEF_REDUC_BITWISE (uint32_t, ior, |=, 16)
|
||||
DEF_REDUC_BITWISE (uint32_t, ior, |=, 32)
|
||||
DEF_REDUC_BITWISE (uint32_t, ior, |=, 64)
|
||||
DEF_REDUC_BITWISE (uint32_t, ior, |=, 128)
|
||||
DEF_REDUC_BITWISE (uint32_t, ior, |=, 256)
|
||||
DEF_REDUC_BITWISE (uint32_t, ior, |=, 512)
|
||||
DEF_REDUC_BITWISE (uint32_t, ior, |=, 1024)
|
||||
|
||||
DEF_REDUC_BITWISE (int32_t, xor, ^=, 4)
|
||||
DEF_REDUC_BITWISE (int32_t, xor, ^=, 8)
|
||||
DEF_REDUC_BITWISE (int32_t, xor, ^=, 16)
|
||||
DEF_REDUC_BITWISE (int32_t, xor, ^=, 32)
|
||||
DEF_REDUC_BITWISE (int32_t, xor, ^=, 64)
|
||||
DEF_REDUC_BITWISE (int32_t, xor, ^=, 128)
|
||||
DEF_REDUC_BITWISE (int32_t, xor, ^=, 256)
|
||||
DEF_REDUC_BITWISE (int32_t, xor, ^=, 512)
|
||||
DEF_REDUC_BITWISE (int32_t, xor, ^=, 1024)
|
||||
|
||||
DEF_REDUC_BITWISE (uint32_t, xor, ^=, 4)
|
||||
DEF_REDUC_BITWISE (uint32_t, xor, ^=, 8)
|
||||
DEF_REDUC_BITWISE (uint32_t, xor, ^=, 16)
|
||||
DEF_REDUC_BITWISE (uint32_t, xor, ^=, 32)
|
||||
DEF_REDUC_BITWISE (uint32_t, xor, ^=, 64)
|
||||
DEF_REDUC_BITWISE (uint32_t, xor, ^=, 128)
|
||||
DEF_REDUC_BITWISE (uint32_t, xor, ^=, 256)
|
||||
DEF_REDUC_BITWISE (uint32_t, xor, ^=, 512)
|
||||
DEF_REDUC_BITWISE (uint32_t, xor, ^=, 1024)
|
||||
|
||||
/* { dg-final { scan-assembler-times {vredand\.vs} 18 } } */
|
||||
/* { dg-final { scan-assembler-times {vredor\.vs} 18 } } */
|
||||
/* { dg-final { scan-assembler-times {vredxor\.vs} 18 } } */
|
||||
/* { dg-final { scan-assembler-not {csrr} } } */
|
||||
63
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-18.c
Normal file
63
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-18.c
Normal file
|
|
@ -0,0 +1,63 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
|
||||
|
||||
#include "def.h"
|
||||
|
||||
DEF_REDUC_BITWISE (int64_t, and, &=, 4)
|
||||
DEF_REDUC_BITWISE (int64_t, and, &=, 8)
|
||||
DEF_REDUC_BITWISE (int64_t, and, &=, 16)
|
||||
DEF_REDUC_BITWISE (int64_t, and, &=, 32)
|
||||
DEF_REDUC_BITWISE (int64_t, and, &=, 64)
|
||||
DEF_REDUC_BITWISE (int64_t, and, &=, 128)
|
||||
DEF_REDUC_BITWISE (int64_t, and, &=, 256)
|
||||
DEF_REDUC_BITWISE (int64_t, and, &=, 512)
|
||||
|
||||
DEF_REDUC_BITWISE (uint64_t, and, &=, 4)
|
||||
DEF_REDUC_BITWISE (uint64_t, and, &=, 8)
|
||||
DEF_REDUC_BITWISE (uint64_t, and, &=, 16)
|
||||
DEF_REDUC_BITWISE (uint64_t, and, &=, 32)
|
||||
DEF_REDUC_BITWISE (uint64_t, and, &=, 64)
|
||||
DEF_REDUC_BITWISE (uint64_t, and, &=, 128)
|
||||
DEF_REDUC_BITWISE (uint64_t, and, &=, 256)
|
||||
DEF_REDUC_BITWISE (uint64_t, and, &=, 512)
|
||||
|
||||
DEF_REDUC_BITWISE (int64_t, ior, |=, 4)
|
||||
DEF_REDUC_BITWISE (int64_t, ior, |=, 8)
|
||||
DEF_REDUC_BITWISE (int64_t, ior, |=, 16)
|
||||
DEF_REDUC_BITWISE (int64_t, ior, |=, 32)
|
||||
DEF_REDUC_BITWISE (int64_t, ior, |=, 64)
|
||||
DEF_REDUC_BITWISE (int64_t, ior, |=, 128)
|
||||
DEF_REDUC_BITWISE (int64_t, ior, |=, 256)
|
||||
DEF_REDUC_BITWISE (int64_t, ior, |=, 512)
|
||||
|
||||
DEF_REDUC_BITWISE (uint64_t, ior, |=, 4)
|
||||
DEF_REDUC_BITWISE (uint64_t, ior, |=, 8)
|
||||
DEF_REDUC_BITWISE (uint64_t, ior, |=, 16)
|
||||
DEF_REDUC_BITWISE (uint64_t, ior, |=, 32)
|
||||
DEF_REDUC_BITWISE (uint64_t, ior, |=, 64)
|
||||
DEF_REDUC_BITWISE (uint64_t, ior, |=, 128)
|
||||
DEF_REDUC_BITWISE (uint64_t, ior, |=, 256)
|
||||
DEF_REDUC_BITWISE (uint64_t, ior, |=, 512)
|
||||
|
||||
DEF_REDUC_BITWISE (int64_t, xor, ^=, 4)
|
||||
DEF_REDUC_BITWISE (int64_t, xor, ^=, 8)
|
||||
DEF_REDUC_BITWISE (int64_t, xor, ^=, 16)
|
||||
DEF_REDUC_BITWISE (int64_t, xor, ^=, 32)
|
||||
DEF_REDUC_BITWISE (int64_t, xor, ^=, 64)
|
||||
DEF_REDUC_BITWISE (int64_t, xor, ^=, 128)
|
||||
DEF_REDUC_BITWISE (int64_t, xor, ^=, 256)
|
||||
DEF_REDUC_BITWISE (int64_t, xor, ^=, 512)
|
||||
|
||||
DEF_REDUC_BITWISE (uint64_t, xor, ^=, 4)
|
||||
DEF_REDUC_BITWISE (uint64_t, xor, ^=, 8)
|
||||
DEF_REDUC_BITWISE (uint64_t, xor, ^=, 16)
|
||||
DEF_REDUC_BITWISE (uint64_t, xor, ^=, 32)
|
||||
DEF_REDUC_BITWISE (uint64_t, xor, ^=, 64)
|
||||
DEF_REDUC_BITWISE (uint64_t, xor, ^=, 128)
|
||||
DEF_REDUC_BITWISE (uint64_t, xor, ^=, 256)
|
||||
DEF_REDUC_BITWISE (uint64_t, xor, ^=, 512)
|
||||
|
||||
/* { dg-final { scan-assembler-times {vredand\.vs} 16 } } */
|
||||
/* { dg-final { scan-assembler-times {vredor\.vs} 16 } } */
|
||||
/* { dg-final { scan-assembler-times {vredxor\.vs} 16 } } */
|
||||
/* { dg-final { scan-assembler-not {csrr} } } */
|
||||
18
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-19.c
Normal file
18
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-19.c
Normal file
|
|
@ -0,0 +1,18 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
|
||||
|
||||
#include "def.h"
|
||||
|
||||
DEF_REDUC_PLUS (_Float16, 4)
|
||||
DEF_REDUC_PLUS (_Float16, 8)
|
||||
DEF_REDUC_PLUS (_Float16, 16)
|
||||
DEF_REDUC_PLUS (_Float16, 32)
|
||||
DEF_REDUC_PLUS (_Float16, 64)
|
||||
DEF_REDUC_PLUS (_Float16, 128)
|
||||
DEF_REDUC_PLUS (_Float16, 256)
|
||||
DEF_REDUC_PLUS (_Float16, 512)
|
||||
DEF_REDUC_PLUS (_Float16, 1024)
|
||||
DEF_REDUC_PLUS (_Float16, 2048)
|
||||
|
||||
/* { dg-final { scan-assembler-times {vfredosum\.vs} 10 } } */
|
||||
/* { dg-final { scan-assembler-not {csrr} } } */
|
||||
29
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-2.c
Normal file
29
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-2.c
Normal file
|
|
@ -0,0 +1,29 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
|
||||
|
||||
#include "def.h"
|
||||
|
||||
DEF_REDUC_PLUS (int16_t, 4)
|
||||
DEF_REDUC_PLUS (int16_t, 8)
|
||||
DEF_REDUC_PLUS (int16_t, 16)
|
||||
DEF_REDUC_PLUS (int16_t, 32)
|
||||
DEF_REDUC_PLUS (int16_t, 64)
|
||||
DEF_REDUC_PLUS (int16_t, 128)
|
||||
DEF_REDUC_PLUS (int16_t, 256)
|
||||
DEF_REDUC_PLUS (int16_t, 512)
|
||||
DEF_REDUC_PLUS (int16_t, 1024)
|
||||
DEF_REDUC_PLUS (int16_t, 2048)
|
||||
|
||||
DEF_REDUC_PLUS (uint16_t, 4)
|
||||
DEF_REDUC_PLUS (uint16_t, 8)
|
||||
DEF_REDUC_PLUS (uint16_t, 16)
|
||||
DEF_REDUC_PLUS (uint16_t, 32)
|
||||
DEF_REDUC_PLUS (uint16_t, 64)
|
||||
DEF_REDUC_PLUS (uint16_t, 128)
|
||||
DEF_REDUC_PLUS (uint16_t, 256)
|
||||
DEF_REDUC_PLUS (uint16_t, 512)
|
||||
DEF_REDUC_PLUS (uint16_t, 1024)
|
||||
DEF_REDUC_PLUS (uint16_t, 2048)
|
||||
|
||||
/* { dg-final { scan-assembler-times {vredsum\.vs} 20 } } */
|
||||
/* { dg-final { scan-assembler-not {csrr} } } */
|
||||
17
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-20.c
Normal file
17
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-20.c
Normal file
|
|
@ -0,0 +1,17 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
|
||||
|
||||
#include "def.h"
|
||||
|
||||
DEF_REDUC_PLUS (float, 4)
|
||||
DEF_REDUC_PLUS (float, 8)
|
||||
DEF_REDUC_PLUS (float, 16)
|
||||
DEF_REDUC_PLUS (float, 32)
|
||||
DEF_REDUC_PLUS (float, 64)
|
||||
DEF_REDUC_PLUS (float, 128)
|
||||
DEF_REDUC_PLUS (float, 256)
|
||||
DEF_REDUC_PLUS (float, 512)
|
||||
DEF_REDUC_PLUS (float, 1024)
|
||||
|
||||
/* { dg-final { scan-assembler-times {vfredosum\.vs} 9 } } */
|
||||
/* { dg-final { scan-assembler-not {csrr} } } */
|
||||
16
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-21.c
Normal file
16
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-21.c
Normal file
|
|
@ -0,0 +1,16 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
|
||||
|
||||
#include "def.h"
|
||||
|
||||
DEF_REDUC_PLUS (float, 4)
|
||||
DEF_REDUC_PLUS (float, 8)
|
||||
DEF_REDUC_PLUS (float, 16)
|
||||
DEF_REDUC_PLUS (float, 32)
|
||||
DEF_REDUC_PLUS (float, 64)
|
||||
DEF_REDUC_PLUS (float, 128)
|
||||
DEF_REDUC_PLUS (float, 256)
|
||||
DEF_REDUC_PLUS (float, 512)
|
||||
|
||||
/* { dg-final { scan-assembler-times {vfredosum\.vs} 8 } } */
|
||||
/* { dg-final { scan-assembler-not {csrr} } } */
|
||||
27
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-3.c
Normal file
27
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-3.c
Normal file
|
|
@ -0,0 +1,27 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
|
||||
|
||||
#include "def.h"
|
||||
|
||||
DEF_REDUC_PLUS (int32_t, 4)
|
||||
DEF_REDUC_PLUS (int32_t, 8)
|
||||
DEF_REDUC_PLUS (int32_t, 16)
|
||||
DEF_REDUC_PLUS (int32_t, 32)
|
||||
DEF_REDUC_PLUS (int32_t, 64)
|
||||
DEF_REDUC_PLUS (int32_t, 128)
|
||||
DEF_REDUC_PLUS (int32_t, 256)
|
||||
DEF_REDUC_PLUS (int32_t, 512)
|
||||
DEF_REDUC_PLUS (int32_t, 1024)
|
||||
|
||||
DEF_REDUC_PLUS (uint32_t, 4)
|
||||
DEF_REDUC_PLUS (uint32_t, 8)
|
||||
DEF_REDUC_PLUS (uint32_t, 16)
|
||||
DEF_REDUC_PLUS (uint32_t, 32)
|
||||
DEF_REDUC_PLUS (uint32_t, 64)
|
||||
DEF_REDUC_PLUS (uint32_t, 128)
|
||||
DEF_REDUC_PLUS (uint32_t, 256)
|
||||
DEF_REDUC_PLUS (uint32_t, 512)
|
||||
DEF_REDUC_PLUS (uint32_t, 1024)
|
||||
|
||||
/* { dg-final { scan-assembler-times {vredsum\.vs} 18 } } */
|
||||
/* { dg-final { scan-assembler-not {csrr} } } */
|
||||
25
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-4.c
Normal file
25
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-4.c
Normal file
|
|
@ -0,0 +1,25 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
|
||||
|
||||
#include "def.h"
|
||||
|
||||
DEF_REDUC_PLUS (int64_t, 4)
|
||||
DEF_REDUC_PLUS (int64_t, 8)
|
||||
DEF_REDUC_PLUS (int64_t, 16)
|
||||
DEF_REDUC_PLUS (int64_t, 32)
|
||||
DEF_REDUC_PLUS (int64_t, 64)
|
||||
DEF_REDUC_PLUS (int64_t, 128)
|
||||
DEF_REDUC_PLUS (int64_t, 256)
|
||||
DEF_REDUC_PLUS (int64_t, 512)
|
||||
|
||||
DEF_REDUC_PLUS (uint64_t, 4)
|
||||
DEF_REDUC_PLUS (uint64_t, 8)
|
||||
DEF_REDUC_PLUS (uint64_t, 16)
|
||||
DEF_REDUC_PLUS (uint64_t, 32)
|
||||
DEF_REDUC_PLUS (uint64_t, 64)
|
||||
DEF_REDUC_PLUS (uint64_t, 128)
|
||||
DEF_REDUC_PLUS (uint64_t, 256)
|
||||
DEF_REDUC_PLUS (uint64_t, 512)
|
||||
|
||||
/* { dg-final { scan-assembler-times {vredsum\.vs} 16 } } */
|
||||
/* { dg-final { scan-assembler-not {csrr} } } */
|
||||
18
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-5.c
Normal file
18
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-5.c
Normal file
|
|
@ -0,0 +1,18 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math" } */
|
||||
|
||||
#include "def.h"
|
||||
|
||||
DEF_REDUC_PLUS (_Float16, 4)
|
||||
DEF_REDUC_PLUS (_Float16, 8)
|
||||
DEF_REDUC_PLUS (_Float16, 16)
|
||||
DEF_REDUC_PLUS (_Float16, 32)
|
||||
DEF_REDUC_PLUS (_Float16, 64)
|
||||
DEF_REDUC_PLUS (_Float16, 128)
|
||||
DEF_REDUC_PLUS (_Float16, 256)
|
||||
DEF_REDUC_PLUS (_Float16, 512)
|
||||
DEF_REDUC_PLUS (_Float16, 1024)
|
||||
DEF_REDUC_PLUS (_Float16, 2048)
|
||||
|
||||
/* { dg-final { scan-assembler-times {vfredusum\.vs} 10 } } */
|
||||
/* { dg-final { scan-assembler-not {csrr} } } */
|
||||
17
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-6.c
Normal file
17
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-6.c
Normal file
|
|
@ -0,0 +1,17 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math" } */
|
||||
|
||||
#include "def.h"
|
||||
|
||||
DEF_REDUC_PLUS (float, 4)
|
||||
DEF_REDUC_PLUS (float, 8)
|
||||
DEF_REDUC_PLUS (float, 16)
|
||||
DEF_REDUC_PLUS (float, 32)
|
||||
DEF_REDUC_PLUS (float, 64)
|
||||
DEF_REDUC_PLUS (float, 128)
|
||||
DEF_REDUC_PLUS (float, 256)
|
||||
DEF_REDUC_PLUS (float, 512)
|
||||
DEF_REDUC_PLUS (float, 1024)
|
||||
|
||||
/* { dg-final { scan-assembler-times {vfredusum\.vs} 9 } } */
|
||||
/* { dg-final { scan-assembler-not {csrr} } } */
|
||||
16
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-7.c
Normal file
16
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-7.c
Normal file
|
|
@ -0,0 +1,16 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math" } */
|
||||
|
||||
#include "def.h"
|
||||
|
||||
DEF_REDUC_PLUS (double, 4)
|
||||
DEF_REDUC_PLUS (double, 8)
|
||||
DEF_REDUC_PLUS (double, 16)
|
||||
DEF_REDUC_PLUS (double, 32)
|
||||
DEF_REDUC_PLUS (double, 64)
|
||||
DEF_REDUC_PLUS (double, 128)
|
||||
DEF_REDUC_PLUS (double, 256)
|
||||
DEF_REDUC_PLUS (double, 512)
|
||||
|
||||
/* { dg-final { scan-assembler-times {vfredusum\.vs} 8 } } */
|
||||
/* { dg-final { scan-assembler-not {csrr} } } */
|
||||
58
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-8.c
Normal file
58
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-8.c
Normal file
|
|
@ -0,0 +1,58 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
|
||||
|
||||
#include "def.h"
|
||||
|
||||
DEF_REDUC_MAXMIN (int8_t, max, >, 4)
|
||||
DEF_REDUC_MAXMIN (int8_t, max, >, 8)
|
||||
DEF_REDUC_MAXMIN (int8_t, max, >, 16)
|
||||
DEF_REDUC_MAXMIN (int8_t, max, >, 32)
|
||||
DEF_REDUC_MAXMIN (int8_t, max, >, 64)
|
||||
DEF_REDUC_MAXMIN (int8_t, max, >, 128)
|
||||
DEF_REDUC_MAXMIN (int8_t, max, >, 256)
|
||||
DEF_REDUC_MAXMIN (int8_t, max, >, 512)
|
||||
DEF_REDUC_MAXMIN (int8_t, max, >, 1024)
|
||||
DEF_REDUC_MAXMIN (int8_t, max, >, 2048)
|
||||
DEF_REDUC_MAXMIN (int8_t, max, >, 4096)
|
||||
|
||||
DEF_REDUC_MAXMIN (uint8_t, max, >, 4)
|
||||
DEF_REDUC_MAXMIN (uint8_t, max, >, 8)
|
||||
DEF_REDUC_MAXMIN (uint8_t, max, >, 16)
|
||||
DEF_REDUC_MAXMIN (uint8_t, max, >, 32)
|
||||
DEF_REDUC_MAXMIN (uint8_t, max, >, 64)
|
||||
DEF_REDUC_MAXMIN (uint8_t, max, >, 128)
|
||||
DEF_REDUC_MAXMIN (uint8_t, max, >, 256)
|
||||
DEF_REDUC_MAXMIN (uint8_t, max, >, 512)
|
||||
DEF_REDUC_MAXMIN (uint8_t, max, >, 1024)
|
||||
DEF_REDUC_MAXMIN (uint8_t, max, >, 2048)
|
||||
DEF_REDUC_MAXMIN (uint8_t, max, >, 4096)
|
||||
|
||||
DEF_REDUC_MAXMIN (int8_t, min, <, 4)
|
||||
DEF_REDUC_MAXMIN (int8_t, min, <, 8)
|
||||
DEF_REDUC_MAXMIN (int8_t, min, <, 16)
|
||||
DEF_REDUC_MAXMIN (int8_t, min, <, 32)
|
||||
DEF_REDUC_MAXMIN (int8_t, min, <, 64)
|
||||
DEF_REDUC_MAXMIN (int8_t, min, <, 128)
|
||||
DEF_REDUC_MAXMIN (int8_t, min, <, 256)
|
||||
DEF_REDUC_MAXMIN (int8_t, min, <, 512)
|
||||
DEF_REDUC_MAXMIN (int8_t, min, <, 1024)
|
||||
DEF_REDUC_MAXMIN (int8_t, min, <, 2048)
|
||||
DEF_REDUC_MAXMIN (int8_t, min, <, 4096)
|
||||
|
||||
DEF_REDUC_MAXMIN (uint8_t, min, <, 4)
|
||||
DEF_REDUC_MAXMIN (uint8_t, min, <, 8)
|
||||
DEF_REDUC_MAXMIN (uint8_t, min, <, 16)
|
||||
DEF_REDUC_MAXMIN (uint8_t, min, <, 32)
|
||||
DEF_REDUC_MAXMIN (uint8_t, min, <, 64)
|
||||
DEF_REDUC_MAXMIN (uint8_t, min, <, 128)
|
||||
DEF_REDUC_MAXMIN (uint8_t, min, <, 256)
|
||||
DEF_REDUC_MAXMIN (uint8_t, min, <, 512)
|
||||
DEF_REDUC_MAXMIN (uint8_t, min, <, 1024)
|
||||
DEF_REDUC_MAXMIN (uint8_t, min, <, 2048)
|
||||
DEF_REDUC_MAXMIN (uint8_t, min, <, 4096)
|
||||
|
||||
/* { dg-final { scan-assembler-times {vredmax\.vs} 11 } } */
|
||||
/* { dg-final { scan-assembler-times {vredmaxu\.vs} 11 } } */
|
||||
/* { dg-final { scan-assembler-times {vredmin\.vs} 11 } } */
|
||||
/* { dg-final { scan-assembler-times {vredminu\.vs} 11 } } */
|
||||
/* { dg-final { scan-assembler-not {csrr} } } */
|
||||
54
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-9.c
Normal file
54
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/reduc-9.c
Normal file
|
|
@ -0,0 +1,54 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8" } */
|
||||
|
||||
#include "def.h"
|
||||
|
||||
DEF_REDUC_MAXMIN (int16_t, max, >, 4)
|
||||
DEF_REDUC_MAXMIN (int16_t, max, >, 8)
|
||||
DEF_REDUC_MAXMIN (int16_t, max, >, 16)
|
||||
DEF_REDUC_MAXMIN (int16_t, max, >, 32)
|
||||
DEF_REDUC_MAXMIN (int16_t, max, >, 64)
|
||||
DEF_REDUC_MAXMIN (int16_t, max, >, 128)
|
||||
DEF_REDUC_MAXMIN (int16_t, max, >, 256)
|
||||
DEF_REDUC_MAXMIN (int16_t, max, >, 512)
|
||||
DEF_REDUC_MAXMIN (int16_t, max, >, 1024)
|
||||
DEF_REDUC_MAXMIN (int16_t, max, >, 2048)
|
||||
|
||||
DEF_REDUC_MAXMIN (uint16_t, max, >, 4)
|
||||
DEF_REDUC_MAXMIN (uint16_t, max, >, 8)
|
||||
DEF_REDUC_MAXMIN (uint16_t, max, >, 16)
|
||||
DEF_REDUC_MAXMIN (uint16_t, max, >, 32)
|
||||
DEF_REDUC_MAXMIN (uint16_t, max, >, 64)
|
||||
DEF_REDUC_MAXMIN (uint16_t, max, >, 128)
|
||||
DEF_REDUC_MAXMIN (uint16_t, max, >, 256)
|
||||
DEF_REDUC_MAXMIN (uint16_t, max, >, 512)
|
||||
DEF_REDUC_MAXMIN (uint16_t, max, >, 1024)
|
||||
DEF_REDUC_MAXMIN (uint16_t, max, >, 2048)
|
||||
|
||||
DEF_REDUC_MAXMIN (int16_t, min, <, 4)
|
||||
DEF_REDUC_MAXMIN (int16_t, min, <, 8)
|
||||
DEF_REDUC_MAXMIN (int16_t, min, <, 16)
|
||||
DEF_REDUC_MAXMIN (int16_t, min, <, 32)
|
||||
DEF_REDUC_MAXMIN (int16_t, min, <, 64)
|
||||
DEF_REDUC_MAXMIN (int16_t, min, <, 128)
|
||||
DEF_REDUC_MAXMIN (int16_t, min, <, 256)
|
||||
DEF_REDUC_MAXMIN (int16_t, min, <, 512)
|
||||
DEF_REDUC_MAXMIN (int16_t, min, <, 1024)
|
||||
DEF_REDUC_MAXMIN (int16_t, min, <, 2048)
|
||||
|
||||
DEF_REDUC_MAXMIN (uint16_t, min, <, 4)
|
||||
DEF_REDUC_MAXMIN (uint16_t, min, <, 8)
|
||||
DEF_REDUC_MAXMIN (uint16_t, min, <, 16)
|
||||
DEF_REDUC_MAXMIN (uint16_t, min, <, 32)
|
||||
DEF_REDUC_MAXMIN (uint16_t, min, <, 64)
|
||||
DEF_REDUC_MAXMIN (uint16_t, min, <, 128)
|
||||
DEF_REDUC_MAXMIN (uint16_t, min, <, 256)
|
||||
DEF_REDUC_MAXMIN (uint16_t, min, <, 512)
|
||||
DEF_REDUC_MAXMIN (uint16_t, min, <, 1024)
|
||||
DEF_REDUC_MAXMIN (uint16_t, min, <, 2048)
|
||||
|
||||
/* { dg-final { scan-assembler-times {vredmax\.vs} 10 } } */
|
||||
/* { dg-final { scan-assembler-times {vredmaxu\.vs} 10 } } */
|
||||
/* { dg-final { scan-assembler-times {vredmin\.vs} 10 } } */
|
||||
/* { dg-final { scan-assembler-times {vredminu\.vs} 10 } } */
|
||||
/* { dg-final { scan-assembler-not {csrr} } } */
|
||||
Loading…
Add table
Reference in a new issue