rs6000: Remove some vec_extract_even/odd expanders.
The ones that expand to VPERM can be handled by generic code.
The even v4si and v4sf expanders remain until vector.md can be
updated to not invoke them directly.
* config/rs6000/altivec.md (vec_extract_evenv8hi,
vec_extract_evenv16qi, vec_extract_oddv4si,
vec_extract_oddv4sf): Remove.
From-SVN: r180452
This commit is contained in:
Richard Henderson
Richard Henderson
parent
c3a5818eb2
commit
45815441c3
2 changed files with 6 additions and 132 deletions
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@ -1,5 +1,9 @@
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2011-10-25 Richard Henderson <rth@redhat.com>
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* config/rs6000/altivec.md (vec_extract_evenv8hi,
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vec_extract_evenv16qi, vec_extract_oddv4si,
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vec_extract_oddv4sf): Remove.
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* config/spu/spu.md (vec_extract_evenv4si, vec_extract_evenv4sf,
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vec_extract_evenv8hi, vec_extract_evenv16qi, vec_extract_oddv4si,
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vec_extract_oddv4sf, vec_extract_oddv8hi, vec_extract_oddv16qi,
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@ -2429,6 +2429,7 @@
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"stvrxl %1,%y0"
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[(set_attr "type" "vecstore")])
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;; ??? This is still used directly by vector.md
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(define_expand "vec_extract_evenv4si"
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[(set (match_operand:V4SI 0 "register_operand" "")
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(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "")
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@ -2462,6 +2463,7 @@
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DONE;
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}")
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;; ??? This is still used directly by vector.md
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(define_expand "vec_extract_evenv4sf"
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[(set (match_operand:V4SF 0 "register_operand" "")
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(unspec:V4SF [(match_operand:V4SF 1 "register_operand" "")
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@ -2495,138 +2497,6 @@
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DONE;
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}")
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(define_expand "vec_extract_evenv8hi"
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[(set (match_operand:V8HI 0 "register_operand" "")
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(unspec:V8HI [(match_operand:V8HI 1 "register_operand" "")
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(match_operand:V8HI 2 "register_operand" "")]
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UNSPEC_EXTEVEN_V8HI))]
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"TARGET_ALTIVEC"
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"
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{
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rtx mask = gen_reg_rtx (V16QImode);
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rtvec v = rtvec_alloc (16);
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RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, 0);
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RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, 1);
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RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, 4);
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RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, 5);
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RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, 8);
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RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, 9);
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RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, 12);
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RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, 13);
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RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, 16);
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RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, 17);
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RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, 20);
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RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, 21);
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RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, 24);
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RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, 25);
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RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, 28);
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RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, 29);
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emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v)));
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emit_insn (gen_altivec_vperm_v8hi (operands[0], operands[1], operands[2], mask));
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DONE;
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}")
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(define_expand "vec_extract_evenv16qi"
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[(set (match_operand:V16QI 0 "register_operand" "")
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(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "")
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(match_operand:V16QI 2 "register_operand" "")]
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UNSPEC_EXTEVEN_V16QI))]
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"TARGET_ALTIVEC"
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"
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{
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rtx mask = gen_reg_rtx (V16QImode);
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rtvec v = rtvec_alloc (16);
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RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, 0);
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RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, 2);
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RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, 4);
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RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, 6);
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RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, 8);
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RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, 10);
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RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, 12);
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RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, 14);
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RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, 16);
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RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, 18);
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RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, 20);
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RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, 22);
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RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, 24);
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RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, 26);
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RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, 28);
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RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, 30);
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emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v)));
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emit_insn (gen_altivec_vperm_v16qi (operands[0], operands[1], operands[2], mask));
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DONE;
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}")
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(define_expand "vec_extract_oddv4si"
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[(set (match_operand:V4SI 0 "register_operand" "")
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(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "")
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(match_operand:V4SI 2 "register_operand" "")]
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UNSPEC_EXTODD_V4SI))]
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"TARGET_ALTIVEC"
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"
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{
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rtx mask = gen_reg_rtx (V16QImode);
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rtvec v = rtvec_alloc (16);
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RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, 4);
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RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, 5);
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RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, 6);
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RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, 7);
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RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, 12);
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RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, 13);
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RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, 14);
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RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, 15);
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RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, 20);
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RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, 21);
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RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, 22);
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RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, 23);
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RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, 28);
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RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, 29);
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RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, 30);
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RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, 31);
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emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v)));
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emit_insn (gen_altivec_vperm_v4si (operands[0], operands[1], operands[2], mask));
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DONE;
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}")
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(define_expand "vec_extract_oddv4sf"
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[(set (match_operand:V4SF 0 "register_operand" "")
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(unspec:V4SF [(match_operand:V4SF 1 "register_operand" "")
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(match_operand:V4SF 2 "register_operand" "")]
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UNSPEC_EXTODD_V4SF))]
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"TARGET_ALTIVEC"
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"
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{
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rtx mask = gen_reg_rtx (V16QImode);
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rtvec v = rtvec_alloc (16);
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RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, 4);
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RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, 5);
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RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, 6);
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RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, 7);
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RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, 12);
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RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, 13);
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RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, 14);
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RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, 15);
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RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, 20);
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RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, 21);
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RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, 22);
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RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, 23);
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RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, 28);
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RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, 29);
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RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, 30);
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RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, 31);
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emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v)));
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emit_insn (gen_altivec_vperm_v4sf (operands[0], operands[1], operands[2], mask));
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DONE;
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}")
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(define_insn "vpkuhum_nomode"
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[(set (match_operand:V16QI 0 "register_operand" "=v")
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(unspec:V16QI [(match_operand 1 "register_operand" "v")
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