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spu: Remove vec_extract_even/odd and vec_interleave expanders.

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* config/spu/spu.md (vec_extract_evenv4si, vec_extract_evenv4sf,
        vec_extract_evenv8hi, vec_extract_evenv16qi, vec_extract_oddv4si,
        vec_extract_oddv4sf, vec_extract_oddv8hi, vec_extract_oddv16qi,
        vec_interleave_highv4sf, vec_interleave_lowv4sf,
        vec_interleave_highv4si, vec_interleave_lowv4si,
        vec_interleave_highv8hi, vec_interleave_lowv8hi,
        vec_interleave_highv16qi, vec_interleave_lowv16qi): Remove.

From-SVN: r180451
This commit is contained in:
Richard Henderson 2011-10-25 14:30:04 -07:00 • committed by Richard Henderson
parent a6b3dfde4c
commit c3a5818eb2
2 changed files with 8 additions and 433 deletions
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8
gcc/ChangeLog
View file

@ -1,5 +1,13 @@
2011-10-25 Richard Henderson <rth@redhat.com>
* config/spu/spu.md (vec_extract_evenv4si, vec_extract_evenv4sf,
vec_extract_evenv8hi, vec_extract_evenv16qi, vec_extract_oddv4si,
vec_extract_oddv4sf, vec_extract_oddv8hi, vec_extract_oddv16qi,
vec_interleave_highv4sf, vec_interleave_lowv4sf,
vec_interleave_highv4si, vec_interleave_lowv4si,
vec_interleave_highv8hi, vec_interleave_lowv8hi,
vec_interleave_highv16qi, vec_interleave_lowv16qi): Remove.
* expr.c (expand_expr_real_2) [VEC_EXTRACT_EVEN_EXPR]: Use binop.
[VEC_EXTRACT_ODD_EXPR, VEC_INTERLEAVE_HIGH_EXPR]: Likewise.
[VEC_INTERLEAVE_LOW_EXPR]: Likewise.

433
gcc/config/spu/spu.md
View file

@ -4947,439 +4947,6 @@ DONE;
})
(define_expand "vec_extract_evenv4si"
[(set (match_operand:V4SI 0 "spu_reg_operand" "=r")
(vec_concat:V4SI
(vec_select:V2SI
(match_operand:V4SI 1 "spu_reg_operand" "r")
(parallel [(const_int 0)(const_int 2)]))
(vec_select:V2SI
(match_operand:V4SI 2 "spu_reg_operand" "r")
(parallel [(const_int 0)(const_int 2)]))))]
""
"
{
rtx mask = gen_reg_rtx (TImode);
unsigned char arr[16] = {
0x00, 0x01, 0x02, 0x03,
0x08, 0x09, 0x0A, 0x0B,
0x10, 0x11, 0x12, 0x13,
0x18, 0x19, 0x1A, 0x1B};
emit_move_insn (mask, array_to_constant (TImode, arr));
emit_insn (gen_shufb (operands[0], operands[1], operands[2], mask));
DONE;
}")
(define_expand "vec_extract_evenv4sf"
[(set (match_operand:V4SF 0 "spu_reg_operand" "=r")
(vec_concat:V4SF
(vec_select:V2SF
(match_operand:V4SF 1 "spu_reg_operand" "r")
(parallel [(const_int 0)(const_int 2)]))
(vec_select:V2SF
(match_operand:V4SF 2 "spu_reg_operand" "r")
(parallel [(const_int 0)(const_int 2)]))))]
""
"
{
rtx mask = gen_reg_rtx (TImode);
unsigned char arr[16] = {
0x00, 0x01, 0x02, 0x03,
0x08, 0x09, 0x0A, 0x0B,
0x10, 0x11, 0x12, 0x13,
0x18, 0x19, 0x1A, 0x1B};
emit_move_insn (mask, array_to_constant (TImode, arr));
emit_insn (gen_shufb (operands[0], operands[1], operands[2], mask));
DONE;
}")
(define_expand "vec_extract_evenv8hi"
[(set (match_operand:V8HI 0 "spu_reg_operand" "=r")
(vec_concat:V8HI
(vec_select:V4HI
(match_operand:V8HI 1 "spu_reg_operand" "r")
(parallel [(const_int 0)(const_int 2)(const_int 4)(const_int 6)]))
(vec_select:V4HI
(match_operand:V8HI 2 "spu_reg_operand" "r")
(parallel [(const_int 0)(const_int 2)(const_int 4)(const_int 6)]))))]
""
"
{
rtx mask = gen_reg_rtx (TImode);
unsigned char arr[16] = {
0x00, 0x01, 0x04, 0x05,
0x08, 0x09, 0x0C, 0x0D,
0x10, 0x11, 0x14, 0x15,
0x18, 0x19, 0x1C, 0x1D};
emit_move_insn (mask, array_to_constant (TImode, arr));
emit_insn (gen_shufb (operands[0], operands[1], operands[2], mask));
DONE;
}")
(define_expand "vec_extract_evenv16qi"
[(set (match_operand:V16QI 0 "spu_reg_operand" "=r")
(vec_concat:V16QI
(vec_select:V8QI
(match_operand:V16QI 1 "spu_reg_operand" "r")
(parallel [(const_int 0)(const_int 2)(const_int 4)(const_int 6)
(const_int 8)(const_int 10)(const_int 12)(const_int 14)]))
(vec_select:V8QI
(match_operand:V16QI 2 "spu_reg_operand" "r")
(parallel [(const_int 0)(const_int 2)(const_int 4)(const_int 6)
(const_int 8)(const_int 10)(const_int 12)(const_int 14)]))))]
""
"
{
rtx mask = gen_reg_rtx (TImode);
unsigned char arr[16] = {
0x00, 0x02, 0x04, 0x06,
0x08, 0x0A, 0x0C, 0x0E,
0x10, 0x12, 0x14, 0x16,
0x18, 0x1A, 0x1C, 0x1E};
emit_move_insn (mask, array_to_constant (TImode, arr));
emit_insn (gen_shufb (operands[0], operands[1], operands[2], mask));
DONE;
}")
(define_expand "vec_extract_oddv4si"
[(set (match_operand:V4SI 0 "spu_reg_operand" "=r")
(vec_concat:V4SI
(vec_select:V2SI
(match_operand:V4SI 1 "spu_reg_operand" "r")
(parallel [(const_int 1)(const_int 3)]))
(vec_select:V2SI
(match_operand:V4SI 2 "spu_reg_operand" "r")
(parallel [(const_int 1)(const_int 3)]))))]
""
"
{
rtx mask = gen_reg_rtx (TImode);
unsigned char arr[16] = {
0x04, 0x05, 0x06, 0x07,
0x0C, 0x0D, 0x0E, 0x0F,
0x14, 0x15, 0x16, 0x17,
0x1C, 0x1D, 0x1E, 0x1F};
emit_move_insn (mask, array_to_constant (TImode, arr));
emit_insn (gen_shufb (operands[0], operands[1], operands[2], mask));
DONE;
}")
(define_expand "vec_extract_oddv4sf"
[(set (match_operand:V4SF 0 "spu_reg_operand" "=r")
(vec_concat:V4SF
(vec_select:V2SF
(match_operand:V4SF 1 "spu_reg_operand" "r")
(parallel [(const_int 1)(const_int 3)]))
(vec_select:V2SF
(match_operand:V4SF 2 "spu_reg_operand" "r")
(parallel [(const_int 1)(const_int 3)]))))]
""
"
{
rtx mask = gen_reg_rtx (TImode);
unsigned char arr[16] = {
0x04, 0x05, 0x06, 0x07,
0x0C, 0x0D, 0x0E, 0x0F,
0x14, 0x15, 0x16, 0x17,
0x1C, 0x1D, 0x1E, 0x1F};
emit_move_insn (mask, array_to_constant (TImode, arr));
emit_insn (gen_shufb (operands[0], operands[1], operands[2], mask));
DONE;
}")
(define_expand "vec_extract_oddv8hi"
[(set (match_operand:V8HI 0 "spu_reg_operand" "=r")
(vec_concat:V8HI
(vec_select:V4HI
(match_operand:V8HI 1 "spu_reg_operand" "r")
(parallel [(const_int 1)(const_int 3)(const_int 5)(const_int 7)]))
(vec_select:V4HI
(match_operand:V8HI 2 "spu_reg_operand" "r")
(parallel [(const_int 1)(const_int 3)(const_int 5)(const_int 7)]))))]
""
"
{
rtx mask = gen_reg_rtx (TImode);
unsigned char arr[16] = {
0x02, 0x03, 0x06, 0x07,
0x0A, 0x0B, 0x0E, 0x0F,
0x12, 0x13, 0x16, 0x17,
0x1A, 0x1B, 0x1E, 0x1F};
emit_move_insn (mask, array_to_constant (TImode, arr));
emit_insn (gen_shufb (operands[0], operands[1], operands[2], mask));
DONE;
}")
(define_expand "vec_extract_oddv16qi"
[(set (match_operand:V16QI 0 "spu_reg_operand" "=r")
(vec_concat:V16QI
(vec_select:V8QI
(match_operand:V16QI 1 "spu_reg_operand" "r")
(parallel [(const_int 1)(const_int 3)(const_int 5)(const_int 7)
(const_int 9)(const_int 11)(const_int 13)(const_int 15)]))
(vec_select:V8QI
(match_operand:V16QI 2 "spu_reg_operand" "r")
(parallel [(const_int 1)(const_int 3)(const_int 5)(const_int 7)
(const_int 9)(const_int 11)(const_int 13)(const_int 15)]))))]
""
"
{
rtx mask = gen_reg_rtx (TImode);
unsigned char arr[16] = {
0x01, 0x03, 0x05, 0x07,
0x09, 0x0B, 0x0D, 0x0F,
0x11, 0x13, 0x15, 0x17,
0x19, 0x1B, 0x1D, 0x1F};
emit_move_insn (mask, array_to_constant (TImode, arr));
emit_insn (gen_shufb (operands[0], operands[1], operands[2], mask));
DONE;
}")
(define_expand "vec_interleave_highv4sf"
[(set (match_operand:V4SF 0 "spu_reg_operand" "=r")
(vec_select:V4SF
(vec_concat:V4SF
(vec_select:V2SF
(match_operand:V4SF 1 "spu_reg_operand" "r")
(parallel [(const_int 0)(const_int 1)]))
(vec_select:V2SF
(match_operand:V4SF 2 "spu_reg_operand" "r")
(parallel [(const_int 0)(const_int 1)])))
(parallel [(const_int 0)(const_int 2)(const_int 1)(const_int 3)])))]
""
"
{
rtx mask = gen_reg_rtx (TImode);
unsigned char arr[16] = {
0x00, 0x01, 0x02, 0x03,
0x10, 0x11, 0x12, 0x13,
0x04, 0x05, 0x06, 0x07,
0x14, 0x15, 0x16, 0x17};
emit_move_insn (mask, array_to_constant (TImode, arr));
emit_insn (gen_shufb (operands[0], operands[1], operands[2], mask));
DONE;
}")
(define_expand "vec_interleave_lowv4sf"
[(set (match_operand:V4SF 0 "spu_reg_operand" "=r")
(vec_select:V4SF
(vec_concat:V4SF
(vec_select:V2SF
(match_operand:V4SF 1 "spu_reg_operand" "r")
(parallel [(const_int 2)(const_int 3)]))
(vec_select:V2SF
(match_operand:V4SF 2 "spu_reg_operand" "r")
(parallel [(const_int 2)(const_int 3)])))
(parallel [(const_int 0)(const_int 2)(const_int 1)(const_int 3)])))]
""
"
{
rtx mask = gen_reg_rtx (TImode);
unsigned char arr[16] = {
0x08, 0x09, 0x0A, 0x0B,
0x18, 0x19, 0x1A, 0x1B,
0x0C, 0x0D, 0x0E, 0x0F,
0x1C, 0x1D, 0x1E, 0x1F};
emit_move_insn (mask, array_to_constant (TImode, arr));
emit_insn (gen_shufb (operands[0], operands[1], operands[2], mask));
DONE;
}")
(define_expand "vec_interleave_highv4si"
[(set (match_operand:V4SI 0 "spu_reg_operand" "=r")
(vec_select:V4SI
(vec_concat:V4SI
(vec_select:V2SI
(match_operand:V4SI 1 "spu_reg_operand" "r")
(parallel [(const_int 0)(const_int 1)]))
(vec_select:V2SI
(match_operand:V4SI 2 "spu_reg_operand" "r")
(parallel [(const_int 0)(const_int 1)])))
(parallel [(const_int 0)(const_int 2)(const_int 1)(const_int 3)])))]
""
"
{
rtx mask = gen_reg_rtx (TImode);
unsigned char arr[16] = {
0x00, 0x01, 0x02, 0x03,
0x10, 0x11, 0x12, 0x13,
0x04, 0x05, 0x06, 0x07,
0x14, 0x15, 0x16, 0x17};
emit_move_insn (mask, array_to_constant (TImode, arr));
emit_insn (gen_shufb (operands[0], operands[1], operands[2], mask));
DONE;
}")
(define_expand "vec_interleave_lowv4si"
[(set (match_operand:V4SI 0 "spu_reg_operand" "=r")
(vec_select:V4SI
(vec_concat:V4SI
(vec_select:V2SI
(match_operand:V4SI 1 "spu_reg_operand" "r")
(parallel [(const_int 2)(const_int 3)]))
(vec_select:V2SI
(match_operand:V4SI 2 "spu_reg_operand" "r")
(parallel [(const_int 2)(const_int 3)])))
(parallel [(const_int 0)(const_int 2)(const_int 1)(const_int 3)])))]
""
"
{
rtx mask = gen_reg_rtx (TImode);
unsigned char arr[16] = {
0x08, 0x09, 0x0A, 0x0B,
0x18, 0x19, 0x1A, 0x1B,
0x0C, 0x0D, 0x0E, 0x0F,
0x1C, 0x1D, 0x1E, 0x1F};
emit_move_insn (mask, array_to_constant (TImode, arr));
emit_insn (gen_shufb (operands[0], operands[1], operands[2], mask));
DONE;
}")
(define_expand "vec_interleave_highv8hi"
[(set (match_operand:V8HI 0 "spu_reg_operand" "=r")
(vec_select:V8HI
(vec_concat:V8HI
(vec_select:V4HI
(match_operand:V8HI 1 "spu_reg_operand" "r")
(parallel [(const_int 0)(const_int 1)(const_int 2)(const_int 3)]))
(vec_select:V4HI
(match_operand:V8HI 2 "spu_reg_operand" "r")
(parallel [(const_int 0)(const_int 1)(const_int 2)(const_int 3)])))
(parallel [(const_int 0)(const_int 4)(const_int 1)(const_int 5)
(const_int 2)(const_int 6)(const_int 3)(const_int 7)])))]
""
"
{
rtx mask = gen_reg_rtx (TImode);
unsigned char arr[16] = {
0x00, 0x01, 0x10, 0x11,
0x02, 0x03, 0x12, 0x13,
0x04, 0x05, 0x14, 0x15,
0x06, 0x07, 0x16, 0x17};
emit_move_insn (mask, array_to_constant (TImode, arr));
emit_insn (gen_shufb (operands[0], operands[1], operands[2], mask));
DONE;
}")
(define_expand "vec_interleave_lowv8hi"
[(set (match_operand:V8HI 0 "spu_reg_operand" "=r")
(vec_select:V8HI
(vec_concat:V8HI
(vec_select:V4HI
(match_operand:V8HI 1 "spu_reg_operand" "r")
(parallel [(const_int 4)(const_int 5)(const_int 6)(const_int 7)]))
(vec_select:V4HI
(match_operand:V8HI 2 "spu_reg_operand" "r")
(parallel [(const_int 4)(const_int 5)(const_int 6)(const_int 7)])))
(parallel [(const_int 0)(const_int 4)(const_int 1)(const_int 5)
(const_int 2)(const_int 6)(const_int 3)(const_int 7)])))]
""
"
{
rtx mask = gen_reg_rtx (TImode);
unsigned char arr[16] = {
0x08, 0x09, 0x18, 0x19,
0x0A, 0x0B, 0x1A, 0x1B,
0x0C, 0x0D, 0x1C, 0x1D,
0x0E, 0x0F, 0x1E, 0x1F};
emit_move_insn (mask, array_to_constant (TImode, arr));
emit_insn (gen_shufb (operands[0], operands[1], operands[2], mask));
DONE;
}")
(define_expand "vec_interleave_highv16qi"
[(set (match_operand:V16QI 0 "spu_reg_operand" "=r")
(vec_select:V16QI
(vec_concat:V16QI
(vec_select:V8QI
(match_operand:V16QI 1 "spu_reg_operand" "r")
(parallel [(const_int 0)(const_int 1)(const_int 2)(const_int 3)
(const_int 4)(const_int 5)(const_int 6)(const_int 7)]))
(vec_select:V8QI
(match_operand:V16QI 2 "spu_reg_operand" "r")
(parallel [(const_int 0)(const_int 1)(const_int 2)(const_int 3)
(const_int 4)(const_int 5)(const_int 6)(const_int 7)])))
(parallel [(const_int 0)(const_int 8)(const_int 1)(const_int 9)
(const_int 2)(const_int 10)(const_int 3)(const_int 11)
(const_int 4)(const_int 12)(const_int 5)(const_int 13)
(const_int 6)(const_int 14)(const_int 7)(const_int 15)])))]
""
"
{
rtx mask = gen_reg_rtx (TImode);
unsigned char arr[16] = {
0x00, 0x10, 0x01, 0x11,
0x02, 0x12, 0x03, 0x13,
0x04, 0x14, 0x05, 0x15,
0x06, 0x16, 0x07, 0x17};
emit_move_insn (mask, array_to_constant (TImode, arr));
emit_insn (gen_shufb (operands[0], operands[1], operands[2], mask));
DONE;
}")
(define_expand "vec_interleave_lowv16qi"
[(set (match_operand:V16QI 0 "spu_reg_operand" "=r")
(vec_select:V16QI
(vec_concat:V16QI
(vec_select:V8QI
(match_operand:V16QI 1 "spu_reg_operand" "r")
(parallel [(const_int 8)(const_int 9)(const_int 10)(const_int 11)
(const_int 12)(const_int 13)(const_int 14)(const_int 15)]))
(vec_select:V8QI
(match_operand:V16QI 2 "spu_reg_operand" "r")
(parallel [(const_int 8)(const_int 9)(const_int 10)(const_int 11)
(const_int 12)(const_int 13)(const_int 14)(const_int 15)])))
(parallel [(const_int 0)(const_int 8)(const_int 1)(const_int 9)
(const_int 2)(const_int 10)(const_int 3)(const_int 11)
(const_int 4)(const_int 12)(const_int 5)(const_int 13)
(const_int 6)(const_int 14)(const_int 7)(const_int 15)])))]
""
"
{
rtx mask = gen_reg_rtx (TImode);
unsigned char arr[16] = {
0x08, 0x18, 0x09, 0x19,
0x0A, 0x1A, 0x0B, 0x1B,
0x0C, 0x1C, 0x0D, 0x1D,
0x0E, 0x1E, 0x0F, 0x1F};
emit_move_insn (mask, array_to_constant (TImode, arr));
emit_insn (gen_shufb (operands[0], operands[1], operands[2], mask));
DONE;
}")
(define_expand "vec_pack_trunc_v8hi"
[(set (match_operand:V16QI 0 "spu_reg_operand" "=r")
(vec_concat:V16QI