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RISC-V: Add COND_LEN_FNMA/COND_LEN_FMS/COND_LEN_FNMS testcases

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This patch is depending on middle-end patch:
https://gcc.gnu.org/pipermail/gcc-patches/2023-August/627621.html

We already had COND_LEN_FNMA/COND_LEN_FMS/COND_FNMS patterns.

Remove TARGET_PREFERRED_ELSE_VALUE since it forbid the COND_LEN_FMS/COND_LEN_FNMS STMT fold.

gcc/ChangeLog:

	* config/riscv/riscv.cc (riscv_preferred_else_value): Remove it since
	it forbid COND_LEN_FMS/COND_LEN_FNMS STMT fold.
	(TARGET_PREFERRED_ELSE_VALUE): Ditto.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv-nofm.c: Adapt test.
	* gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv-nofm.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_fadd-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_fadd-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_fadd-3.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_fadd-4.c: Ditto.
	* gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-3.c: Ditto.
	* gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-10.c: New test.
	* gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-11.c: New test.
	* gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-12.c: New test.
	* gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-4.c: New test.
	* gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-5.c: New test.
	* gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-6.c: New test.
	* gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-7.c: New test.
	* gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-8.c: New test.
	* gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-9.c: New test.
	* gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-10.c: New test.
	* gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-11.c: New test.
	* gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-12.c: New test.
	* gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-4.c: New test.
	* gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-5.c: New test.
	* gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-6.c: New test.
	* gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-7.c: New test.
	* gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-8.c: New test.
	* gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-9.c: New test.
This commit is contained in:
Juzhe-Zhong 2023-08-16 21:20:10 +08:00 • committed by Pan Li
parent a047513c92
commit 1fbcae1c64
27 changed files with 121 additions and 43 deletions
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21
gcc/config/riscv/riscv.cc
View file

@ -8425,24 +8425,6 @@ riscv_vectorize_vec_perm_const (machine_mode vmode, machine_mode op_mode,
return false;
}
/* Implement TARGET_PREFERRED_ELSE_VALUE. For binary operations,
prefer to use the first arithmetic operand as the else value if
the else value doesn't matter, since that exactly matches the RVV
destructive merging form. For ternary operations we could either
pick the first operand and use VMADD-like instructions or the last
operand and use VMACC-like instructions; the latter seems more
natural.
TODO: Currently, the return value is not ideal for RVV since it will
let VSETVL PASS use MU or TU. We will suport undefine value that allows
VSETVL PASS use TA/MA in the future. */
static tree
riscv_preferred_else_value (unsigned, tree, unsigned int nops, tree *ops)
{
return nops == 3 ? ops[2] : ops[0];
}
static bool
riscv_frame_pointer_required (void)
{
@ -8753,9 +8735,6 @@ riscv_frame_pointer_required (void)
#undef TARGET_VECTORIZE_VEC_PERM_CONST
#define TARGET_VECTORIZE_VEC_PERM_CONST riscv_vectorize_vec_perm_const
#undef TARGET_PREFERRED_ELSE_VALUE
#define TARGET_PREFERRED_ELSE_VALUE riscv_preferred_else_value
#undef TARGET_FRAME_POINTER_REQUIRED
#define TARGET_FRAME_POINTER_REQUIRED riscv_frame_pointer_required

7
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv-nofm.c
View file

@ -5,9 +5,6 @@
/* { dg-final { scan-assembler-times {\tvadd\.vv} 16 } } */
/* { dg-final { scan-assembler-times {\tvadd\.vi} 8 } } */
/* { dg-final { scan-assembler-times {\tvfadd\.vv} 7 } } */
/* There are 2 MINUS operations. */
/* { dg-final { scan-assembler-times {\tvfsub\.vv} 2 } } */
/* { dg-final { scan-assembler-times {\tvfadd\.vv} 9 } } */
/* { dg-final { scan-tree-dump-times "\.COND_LEN_ADD" 7 "optimized" } } */
/* { dg-final { scan-tree-dump-times "\.COND_LEN_SUB" 2 "optimized" } } */
/* { dg-final { scan-tree-dump-times "\.COND_LEN_ADD" 9 "optimized" } } */

7
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv-nofm.c
View file

@ -5,9 +5,6 @@
/* { dg-final { scan-assembler-times {\tvadd\.vv} 16 } } */
/* { dg-final { scan-assembler-times {\tvadd\.vi} 8 } } */
/* { dg-final { scan-assembler-times {\tvfadd\.vv} 7 } } */
/* There are 2 MINUS operations. */
/* { dg-final { scan-assembler-times {\tvfsub\.vv} 2 } } */
/* { dg-final { scan-assembler-times {\tvfadd\.vv} 9 } } */
/* { dg-final { scan-tree-dump-times "\.COND_LEN_ADD" 7 "optimized" } } */
/* { dg-final { scan-tree-dump-times "\.COND_LEN_SUB" 2 "optimized" } } */
/* { dg-final { scan-tree-dump-times "\.COND_LEN_ADD" 9 "optimized" } } */

3
gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-1.c
View file

@ -29,5 +29,4 @@
TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times {vfadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 9 } } */
/* { dg-final { scan-assembler-times {vfsub\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 9 } } */
/* { dg-final { scan-assembler-times {vfadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 18 } } */

3
gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-2.c
View file

@ -28,5 +28,4 @@
TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times {vfadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 6 } } */
/* { dg-final { scan-assembler-times {vfsub\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 6 } } */
/* { dg-final { scan-assembler-times {vfadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 12 } } */

3
gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-3.c
View file

@ -29,5 +29,4 @@
TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times {vfadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 9 } } */
/* { dg-final { scan-assembler-times {vfsub\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 9 } } */
/* { dg-final { scan-assembler-times {vfadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 18 } } */

3
gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-4.c
View file

@ -29,5 +29,4 @@
TEST_ALL (DEF_LOOP)
/* { dg-final { scan-assembler-times {vfadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 9 } } */
/* { dg-final { scan-assembler-times {vfsub\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 9 } } */
/* { dg-final { scan-assembler-times {vfadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 18 } } */

4
gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-1.c
View file

@ -3,5 +3,7 @@
#include "ternop-1.c"
/* { dg-final { scan-assembler-not {\tvmv} } } */
/* TODO: we don't have undefine IR for COND_LEN_* operations,
which will produce redundant move instructions here.
Will add assembler-not check of 'vmv' instructions in the future. */
/* { dg-final { scan-tree-dump-times "COND_LEN_FMA" 3 "optimized" } } */

9
gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-10.c Normal file
View file

@ -0,0 +1,9 @@
/* { dg-do compile } */
/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */
#include "ternop-10.c"
/* TODO: we don't have undefine IR for COND_LEN_* operations,
which will produce redundant move instructions here.
Will add assembler-not check of 'vmv' instructions in the future. */
/* { dg-final { scan-tree-dump-times "COND_LEN_FNMS" 3 "optimized" } } */

9
gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-11.c Normal file
View file

@ -0,0 +1,9 @@
/* { dg-do compile } */
/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */
#include "ternop-11.c"
/* TODO: we don't have undefine IR for COND_LEN_* operations,
which will produce redundant move instructions here.
Will add assembler-not check of 'vmv' instructions in the future. */
/* { dg-final { scan-tree-dump-times "COND_LEN_FNMS" 3 "optimized" } } */

6
gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-12.c Normal file
View file

@ -0,0 +1,6 @@
/* { dg-do compile } */
/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details -fno-schedule-insns" } */
#include "ternop-12.c"
/* { dg-final { scan-tree-dump-times "COND_LEN_FNMS" 3 "optimized" } } */

5
gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-3.c
View file

@ -4,6 +4,5 @@
#include "ternop-3.c"
/* { dg-final { scan-assembler-times {\tvmacc\.vv} 8 } } */
/* { dg-final { scan-assembler-times {\tvfmacc\.vv} 6 } } */
/* { dg-final { scan-assembler-times {\tvmv} 11 } } */
/* { dg-final { scan-tree-dump-times "COND_LEN_FMA" 6 "optimized" } } */
/* { dg-final { scan-assembler-times {\tvfmacc\.vv} 9 } } */
/* { dg-final { scan-tree-dump-times "COND_LEN_FMA" 9 "optimized" } } */

9
gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-4.c Normal file
View file

@ -0,0 +1,9 @@
/* { dg-do compile } */
/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */
#include "ternop-4.c"
/* TODO: we don't have undefine IR for COND_LEN_* operations,
which will produce redundant move instructions here.
Will add assembler-not check of 'vmv' instructions in the future. */
/* { dg-final { scan-tree-dump-times "COND_LEN_FNMA" 3 "optimized" } } */

9
gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-5.c Normal file
View file

@ -0,0 +1,9 @@
/* { dg-do compile } */
/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */
#include "ternop-5.c"
/* TODO: we don't have undefine IR for COND_LEN_* operations,
which will produce redundant move instructions here.
Will add assembler-not check of 'vmv' instructions in the future. */
/* { dg-final { scan-tree-dump-times "COND_LEN_FNMA" 3 "optimized" } } */

6
gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-6.c Normal file
View file

@ -0,0 +1,6 @@
/* { dg-do compile } */
/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details -fno-schedule-insns" } */
#include "ternop-6.c"
/* { dg-final { scan-tree-dump-times "COND_LEN_FNMA" 3 "optimized" } } */

9
gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-7.c Normal file
View file

@ -0,0 +1,9 @@
/* { dg-do compile } */
/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */
#include "ternop-7.c"
/* TODO: we don't have undefine IR for COND_LEN_* operations,
which will produce redundant move instructions here.
Will add assembler-not check of 'vmv' instructions in the future. */
/* { dg-final { scan-tree-dump-times "COND_LEN_FMS" 3 "optimized" } } */

9
gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-8.c Normal file
View file

@ -0,0 +1,9 @@
/* { dg-do compile } */
/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details" } */
#include "ternop-8.c"
/* TODO: we don't have undefine IR for COND_LEN_* operations,
which will produce redundant move instructions here.
Will add assembler-not check of 'vmv' instructions in the future. */
/* { dg-final { scan-tree-dump-times "COND_LEN_FMS" 9 "optimized" } } */

6
gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-9.c Normal file
View file

@ -0,0 +1,6 @@
/* { dg-do compile } */
/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fdump-tree-optimized-details -fno-schedule-insns" } */
#include "ternop-9.c"
/* { dg-final { scan-tree-dump-times "COND_LEN_FMS" 9 "optimized" } } */

4
gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-10.c Normal file
View file

@ -0,0 +1,4 @@
/* { dg-do run { target { riscv_vector } } } */
/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */
#include "ternop_run-10.c"

4
gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-11.c Normal file
View file

@ -0,0 +1,4 @@
/* { dg-do run { target { riscv_vector } } } */
/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */
#include "ternop_run-11.c"

4
gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-12.c Normal file
View file

@ -0,0 +1,4 @@
/* { dg-do run { target { riscv_vector } } } */
/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */
#include "ternop_run-12.c"

4
gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-4.c Normal file
View file

@ -0,0 +1,4 @@
/* { dg-do run { target { riscv_vector } } } */
/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */
#include "ternop_run-4.c"

4
gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-5.c Normal file
View file

@ -0,0 +1,4 @@
/* { dg-do run { target { riscv_vector } } } */
/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */
#include "ternop_run-5.c"

4
gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-6.c Normal file
View file

@ -0,0 +1,4 @@
/* { dg-do run { target { riscv_vector } } } */
/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */
#include "ternop_run-6.c"

4
gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-7.c Normal file
View file

@ -0,0 +1,4 @@
/* { dg-do run { target { riscv_vector } } } */
/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */
#include "ternop_run-7.c"

4
gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-8.c Normal file
View file

@ -0,0 +1,4 @@
/* { dg-do run { target { riscv_vector } } } */
/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */
#include "ternop_run-8.c"

4
gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_nofm_run-9.c Normal file
View file

@ -0,0 +1,4 @@
/* { dg-do run { target { riscv_vector } } } */
/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */
#include "ternop_run-9.c"