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Revert "AVX10.2 ymm rounding: Support vcvtpd2{,u}{dq,qq} intrins"

Browse source 
This reverts commit 508ac49e1a.
This commit is contained in:
Haochen Jiang 2025-03-24 14:24:29 +08:00
parent 99a9e72180
commit 1d15565adb
12 changed files with 6 additions and 303 deletions
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218
gcc/config/i386/avx10_2roundingintrin.h
View file

@ -348,144 +348,6 @@ _mm256_maskz_cvt_roundpd_ps (__mmask8 __U, __m256d __A, const int __R)
(__mmask8) __U,
__R);
}
extern __inline __m128i
__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
_mm256_cvt_roundpd_epi32 (__m256d __A, const int __R)
{
return
(__m128i) __builtin_ia32_cvtpd2dq256_mask_round ((__v4df) __A,
(__v4si)
_mm_undefined_si128 (),
(__mmask8) -1,
__R);
}
extern __inline __m128i
__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
_mm256_mask_cvt_roundpd_epi32 (__m128i __W, __mmask8 __U, __m256d __A,
const int __R)
{
return (__m128i) __builtin_ia32_cvtpd2dq256_mask_round ((__v4df) __A,
(__v4si) __W,
(__mmask8) __U,
__R);
}
extern __inline __m128i
__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
_mm256_maskz_cvt_roundpd_epi32 (__mmask8 __U, __m256d __A, const int __R)
{
return (__m128i) __builtin_ia32_cvtpd2dq256_mask_round ((__v4df) __A,
(__v4si)
_mm_setzero_si128 (),
(__mmask8) __U,
__R);
}
extern __inline __m256i
__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
_mm256_cvt_roundpd_epi64 (__m256d __A, const int __R)
{
return
(__m256i) __builtin_ia32_cvtpd2qq256_mask_round ((__v4df) __A,
(__v4di)
_mm256_setzero_si256 (),
(__mmask8) -1,
__R);
}
extern __inline __m256i
__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
_mm256_mask_cvt_roundpd_epi64 (__m256i __W, __mmask8 __U, __m256d __A,
const int __R)
{
return (__m256i) __builtin_ia32_cvtpd2qq256_mask_round ((__v4df) __A,
(__v4di) __W,
(__mmask8) __U,
__R);
}
extern __inline __m256i
__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
_mm256_maskz_cvt_roundpd_epi64 (__mmask8 __U, __m256d __A, const int __R)
{
return
(__m256i) __builtin_ia32_cvtpd2qq256_mask_round ((__v4df) __A,
(__v4di)
_mm256_setzero_si256 (),
(__mmask8) __U,
__R);
}
extern __inline __m128i
__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
_mm256_cvt_roundpd_epu32 (__m256d __A, const int __R)
{
return
(__m128i) __builtin_ia32_cvtpd2udq256_mask_round ((__v4df) __A,
(__v4si)
_mm_undefined_si128 (),
(__mmask8) -1,
__R);
}
extern __inline __m128i
__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
_mm256_mask_cvt_roundpd_epu32 (__m128i __W, __mmask8 __U, __m256d __A,
const int __R)
{
return (__m128i) __builtin_ia32_cvtpd2udq256_mask_round ((__v4df) __A,
(__v4si) __W,
(__mmask8) __U,
__R);
}
extern __inline __m128i
__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
_mm256_maskz_cvt_roundpd_epu32 (__mmask8 __U, __m256d __A, const int __R)
{
return (__m128i) __builtin_ia32_cvtpd2udq256_mask_round ((__v4df) __A,
(__v4si)
_mm_setzero_si128 (),
(__mmask8) __U,
__R);
}
extern __inline __m256i
__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
_mm256_cvt_roundpd_epu64 (__m256d __A, const int __R)
{
return
(__m256i) __builtin_ia32_cvtpd2uqq256_mask_round ((__v4df) __A,
(__v4di)
_mm256_setzero_si256 (),
(__mmask8) -1,
__R);
}
extern __inline __m256i
__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
_mm256_mask_cvt_roundpd_epu64 (__m256i __W, __mmask8 __U, __m256d __A,
const int __R)
{
return (__m256i) __builtin_ia32_cvtpd2uqq256_mask_round ((__v4df) __A,
(__v4di) __W,
(__mmask8) __U,
__R);
}
extern __inline __m256i
__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
_mm256_maskz_cvt_roundpd_epu64 (__mmask8 __U, __m256d __A, const int __R)
{
return
(__m256i) __builtin_ia32_cvtpd2uqq256_mask_round ((__v4df) __A,
(__v4di)
_mm256_setzero_si256 (),
(__mmask8) __U,
__R);
}
#else
#define _mm256_add_round_pd(A, B, R) \
((__m256d) __builtin_ia32_addpd256_mask_round ((__v4df) (A), \
@ -675,86 +537,6 @@ _mm256_maskz_cvt_roundpd_epu64 (__mmask8 __U, __m256d __A, const int __R)
(_mm_setzero_ps ()), \
(__mmask8) (U), \
(R)))
#define _mm256_cvt_roundpd_epi32(A, R) \
((__m128i) __builtin_ia32_cvtpd2dq256_mask_round ((__v4df) (A), \
(__v4si) \
(_mm_undefined_si128 ()), \
(__mmask8) (-1), \
(R)))
#define _mm256_mask_cvt_roundpd_epi32(W, U, A, R) \
((__m128i) __builtin_ia32_cvtpd2dq256_mask_round ((__v4df) (A), \
(__v4si) (W), \
(__mmask8) (U), \
(R)))
#define _mm256_maskz_cvt_roundpd_epi32(U, A, R)\
((__m128i) __builtin_ia32_cvtpd2dq256_mask_round ((__v4df) (A), \
(__v4si) \
(_mm_setzero_si128 ()), \
(__mmask8) (U), \
(R)))
#define _mm256_cvt_roundpd_epi64(A, R) \
((__m256i) __builtin_ia32_cvtpd2qq256_mask_round ((__v4df) (A), \
(__v4di) \
(_mm256_setzero_si256 ()), \
(__mmask8) (-1), \
(R)))
#define _mm256_mask_cvt_roundpd_epi64(W, U, A, R) \
((__m256i) __builtin_ia32_cvtpd2qq256_mask_round ((__v4df) (A), \
(__v4di) (W), \
(__mmask8) (U), \
(R)))
#define _mm256_maskz_cvt_roundpd_epi64(U, A, R) \
((__m256i) __builtin_ia32_cvtpd2qq256_mask_round ((__v4df) (A), \
(__v4di) \
(_mm256_setzero_si256 ()), \
(__mmask8) (U), \
(R)))
#define _mm256_cvt_roundpd_epu32(A, R) \
((__m128i) __builtin_ia32_cvtpd2udq256_mask_round ((__v4df) (A), \
(__v4si) \
(_mm_undefined_si128 ()), \
(__mmask8) (-1), \
(R)))
#define _mm256_mask_cvt_roundpd_epu32(W, U, A, R) \
((__m128i) __builtin_ia32_cvtpd2udq256_mask_round ((__v4df) (A), \
(__v4si) (W), \
(__mmask8) (U), \
(R)))
#define _mm256_maskz_cvt_roundpd_epu32(U, A, R) \
((__m128i) __builtin_ia32_cvtpd2udq256_mask_round ((__v4df) (A), \
(__v4si) \
(_mm_setzero_si128 ()), \
(__mmask8) (U), \
(R)))
#define _mm256_cvt_roundpd_epu64(A, R) \
((__m256i) __builtin_ia32_cvtpd2uqq256_mask_round ((__v4df) (A), \
(__v4di) \
(_mm256_setzero_si256 ()),\
(__mmask8) (-1), \
(R)))
#define _mm256_mask_cvt_roundpd_epu64(W, U, A, R) \
((__m256i) __builtin_ia32_cvtpd2uqq256_mask_round ((__v4df) (A), \
(__v4di) (W), \
(__mmask8) (U), \
(R)))
#define _mm256_maskz_cvt_roundpd_epu64(U, A, R) \
((__m256i) __builtin_ia32_cvtpd2uqq256_mask_round ((__v4df) (A), \
(__v4di) \
(_mm256_setzero_si256 ()),\
(__mmask8) (U), \
(R)))
#endif
#ifdef __DISABLE_AVX10_2_256__

2
gcc/config/i386/i386-builtin-types.def
View file

@ -1426,8 +1426,6 @@ DEF_FUNCTION_TYPE (V8HF, V8SI, V8HF, UQI, INT)
DEF_FUNCTION_TYPE (V8SF, V8SI, V8SF, UQI, INT)
DEF_FUNCTION_TYPE (V8HF, V4DF, V8HF, UQI, INT)
DEF_FUNCTION_TYPE (V4SF, V4DF, V4SF, UQI, INT)
DEF_FUNCTION_TYPE (V4SI, V4DF, V4SI, UQI, INT)
DEF_FUNCTION_TYPE (V4DI, V4DF, V4DI, UQI, INT)
DEF_FUNCTION_TYPE (V32HF, V16SF, V16SF, V32HF, USI, INT)
DEF_FUNCTION_TYPE (V32HF, V16SF, V16SF, V32HF, USI)
DEF_FUNCTION_TYPE (V16HF, V8SF, V8SF, V16HF, UHI)

4
gcc/config/i386/i386-builtin.def
View file

@ -3670,10 +3670,6 @@ BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx512fp16_vcvtdq2ph_v8si_mask_
BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_floatv8siv8sf2_mask_round, "__builtin_ia32_cvtdq2ps256_mask_round", IX86_BUILTIN_VCVTDQ2PS256_MASK_ROUND, UNKNOWN, (int) V8SF_FTYPE_V8SI_V8SF_UQI_INT)
BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx512fp16_vcvtpd2ph_v4df_mask_round, "__builtin_ia32_vcvtpd2ph256_mask_round", IX86_BUILTIN_VCVTPD2PH256_MASK_ROUND, UNKNOWN, (int) V8HF_FTYPE_V4DF_V8HF_UQI_INT)
BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx_cvtpd2ps256_mask_round, "__builtin_ia32_cvtpd2ps256_mask_round", IX86_BUILTIN_CVTPD2PS256_MASK_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4DF_V4SF_UQI_INT)
BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_avx_cvtpd2dq256_mask_round, "__builtin_ia32_cvtpd2dq256_mask_round", IX86_BUILTIN_CVTPD2DQ256_MASK_ROUND, UNKNOWN, (int) V4SI_FTYPE_V4DF_V4SI_UQI_INT)
BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_fix_notruncv4dfv4di2_mask_round, "__builtin_ia32_cvtpd2qq256_mask_round", IX86_BUILTIN_CVTPD2QQ256_MASK_ROUND, UNKNOWN, (int) V4DI_FTYPE_V4DF_V4DI_UQI_INT)
BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_fixuns_notruncv4dfv4si2_mask_round, "__builtin_ia32_cvtpd2udq256_mask_round", IX86_BUILTIN_CVTPD2UDQ256_MASK_ROUND, UNKNOWN, (int) V4SI_FTYPE_V4DF_V4SI_UQI_INT)
BDESC (0, OPTION_MASK_ISA2_AVX10_2_256, CODE_FOR_fixuns_notruncv4dfv4di2_mask_round, "__builtin_ia32_cvtpd2uqq256_mask_round", IX86_BUILTIN_CVTPD2UQQ256_MASK_ROUND, UNKNOWN, (int) V4DI_FTYPE_V4DF_V4DI_UQI_INT)
BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_avx10_2_cvt2ps2phx_v32hf_mask_round, "__builtin_ia32_vcvt2ps2phx512_mask_round", IX86_BUILTIN_VCVT2PS2PHX_V32HF_MASK_ROUND, UNKNOWN, (int) V32HF_FTYPE_V16SF_V16SF_V32HF_USI_INT)
BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_avx10_2_cvtph2ibsv32hf_mask_round, "__builtin_ia32_cvtph2ibs512_mask_round", IX86_BUILTIN_CVTPH2IBS512_MASK_ROUND, UNKNOWN, (int) V32HI_FTYPE_V32HF_V32HI_USI_INT)
BDESC (0, OPTION_MASK_ISA2_AVX10_2_512, CODE_FOR_avx10_2_cvtph2iubsv32hf_mask_round, "__builtin_ia32_cvtph2iubs512_mask_round", IX86_BUILTIN_CVTPH2IUBS512_MASK_ROUND, UNKNOWN, (int) V32HI_FTYPE_V32HF_V32HI_USI_INT)

2
gcc/config/i386/i386-expand.cc
View file

@ -12750,9 +12750,7 @@ ix86_expand_round_builtin (const struct builtin_description *d,
case V8DF_FTYPE_V8SF_V8DF_QI_INT:
case V16SF_FTYPE_V16HI_V16SF_HI_INT:
case V8SF_FTYPE_V8SI_V8SF_UQI_INT:
case V4DI_FTYPE_V4DF_V4DI_UQI_INT:
case V2DF_FTYPE_V2DF_V2DF_V2DF_INT:
case V4SI_FTYPE_V4DF_V4SI_UQI_INT:
case V4SF_FTYPE_V4DF_V4SF_UQI_INT:
case V4SF_FTYPE_V4SF_V4SF_V4SF_INT:
case V8HF_FTYPE_V8DI_V8HF_UQI_INT:

13
gcc/config/i386/sse.md
View file

@ -9400,13 +9400,12 @@
(set_attr "prefix" "evex")
(set_attr "mode" "OI")])
(define_insn "avx_cvtpd2dq256<mask_name><round_name>"
(define_insn "avx_cvtpd2dq256<mask_name>"
[(set (match_operand:V4SI 0 "register_operand" "=v")
(unspec:V4SI [(match_operand:V4DF 1 "<round_nimm_predicate>" "<round_constraint>")]
(unspec:V4SI [(match_operand:V4DF 1 "nonimmediate_operand" "vm")]
UNSPEC_FIX_NOTRUNC))]
"TARGET_AVX && <mask_avx512vl_condition>
&& (!<round_applied> || TARGET_AVX10_2_256)"
"vcvtpd2dq<round_suff>\t{<round_mask_op2>%1, %0<mask_operand2>|%0<mask_operand2>, %1<round_mask_op2>}"
"TARGET_AVX && <mask_avx512vl_condition>"
"vcvtpd2dq{y}\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
[(set_attr "type" "ssecvt")
(set_attr "prefix" "<mask_prefix>")
(set_attr "mode" "OI")])
@ -9496,8 +9495,8 @@
(unspec:<si2dfmode>
[(match_operand:VF2_512_256VL 1 "nonimmediate_operand" "<round_constraint>")]
UNSPEC_UNSIGNED_FIX_NOTRUNC))]
"TARGET_AVX512F && <round_mode_condition>"
"vcvtpd2udq<round_pd2udqsuff>\t{<round_mask_op2>%1, %0<mask_operand2>|%0<mask_operand2>, %1<round_mask_op2>}"
"TARGET_AVX512F"
"vcvtpd2udq<pd2udqsuff>\t{<round_mask_op2>%1, %0<mask_operand2>|%0<mask_operand2>, %1<round_mask_op2>}"
[(set_attr "type" "ssecvt")
(set_attr "prefix" "evex")
(set_attr "mode" "<sseinsnmode>")])

1
gcc/config/i386/subst.md
View file

@ -199,7 +199,6 @@
(define_subst_attr "round_constraint" "round" "vm" "v")
(define_subst_attr "round_suff" "round" "{y}" "")
(define_subst_attr "round_qq2phsuff" "round" "<qq2phsuff>" "")
(define_subst_attr "round_pd2udqsuff" "round" "<pd2udqsuff>" "")
(define_subst_attr "bcst_round_constraint" "round" "vmBr" "v")
(define_subst_attr "round_constraint2" "round" "m" "v")
(define_subst_attr "round_constraint3" "round" "rm" "r")

4
gcc/testsuite/gcc.target/i386/avx-1.c
View file

@ -853,10 +853,6 @@
#define __builtin_ia32_cvtdq2ps256_mask_round(A, B, C, D) __builtin_ia32_cvtdq2ps256_mask_round(A, B, C, 8)
#define __builtin_ia32_vcvtpd2ph256_mask_round(A, B, C, D) __builtin_ia32_vcvtpd2ph256_mask_round(A, B, C, 8)
#define __builtin_ia32_cvtpd2ps256_mask_round(A, B, C, D) __builtin_ia32_cvtpd2ps256_mask_round(A, B, C, 8)
#define __builtin_ia32_cvtpd2dq256_mask_round(A, B, C, D) __builtin_ia32_cvtpd2dq256_mask_round(A, B, C, 8)
#define __builtin_ia32_cvtpd2qq256_mask_round(A, B, C, D) __builtin_ia32_cvtpd2qq256_mask_round(A, B, C, 8)
#define __builtin_ia32_cvtpd2udq256_mask_round(A, B, C, D) __builtin_ia32_cvtpd2udq256_mask_round(A, B, C, 8)
#define __builtin_ia32_cvtpd2uqq256_mask_round(A, B, C, D) __builtin_ia32_cvtpd2uqq256_mask_round(A, B, C, 8)
/* avx10_2-512mediaintrin.h */
#define __builtin_ia32_mpsadbw512(A, B, C) __builtin_ia32_mpsadbw512 (A, B, 1)

33
gcc/testsuite/gcc.target/i386/avx10_2-rounding-1.c
View file

@ -27,23 +27,10 @@
/* { dg-final { scan-assembler-times "vcvtpd2ps\[ \\t\]+\[^\n\]*\{rn-sae\}\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
/* { dg-final { scan-assembler-times "vcvtpd2ps\[ \\t\]+\[^\n\]*\{rd-sae\}\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
/* { dg-final { scan-assembler-times "vcvtpd2ps\[ \\t\]+\[^\n\]*\{rz-sae\}\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */
/* { dg-final { scan-assembler-times "vcvtpd2dq\[ \\t\]+\[^\n\]*\{rn-sae\}\[^\n\]*%ymm\[0-9\]+\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
/* { dg-final { scan-assembler-times "vcvtpd2dq\[ \\t\]+\[^\n\]*\{ru-sae\}\[^\n\]*%ymm\[0-9\]+\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
/* { dg-final { scan-assembler-times "vcvtpd2dq\[ \\t\]+\[^\n\]*\{rz-sae\}\[^\n\]*%ymm\[0-9\]+\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */
/* { dg-final { scan-assembler-times "vcvtpd2qq\[ \\t\]+\[^\n\]*\{rn-sae\}\[^\{\n\]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
/* { dg-final { scan-assembler-times "vcvtpd2qq\[ \\t\]+\[^\n\]*\{ru-sae\}\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
/* { dg-final { scan-assembler-times "vcvtpd2qq\[ \\t\]+\[^\n\]*\{rz-sae\}\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */
/* { dg-final { scan-assembler-times "vcvtpd2udq\[ \\t\]+\[^\n\]*\{rn-sae\}\[^\n\]*%ymm\[0-9\]+\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
/* { dg-final { scan-assembler-times "vcvtpd2udq\[ \\t\]+\[^\n\]*\{ru-sae\}\[^\n\]*%ymm\[0-9\]+\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
/* { dg-final { scan-assembler-times "vcvtpd2udq\[ \\t\]+\[^\n\]*\{rz-sae\}\[^\n\]*%ymm\[0-9\]+\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */
/* { dg-final { scan-assembler-times "vcvtpd2uqq\[ \\t\]+\[^\n\]*\{rn-sae\}\[^\{\n\]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
/* { dg-final { scan-assembler-times "vcvtpd2uqq\[ \\t\]+\[^\n\]*\{rd-sae\}\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
/* { dg-final { scan-assembler-times "vcvtpd2uqq\[ \\t\]+\[^\n\]*\{rz-sae\}\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */
#include <immintrin.h>
volatile __m128 hx;
volatile __m128i hxi;
volatile __m128h hxh;
volatile __m256 x;
volatile __m256d xd;
@ -105,23 +92,3 @@ avx10_2_test_4 (void)
hx = _mm256_mask_cvt_roundpd_ps (hx, 4, xd, _MM_FROUND_TO_NEG_INF | _MM_FROUND_NO_EXC);
hx = _mm256_maskz_cvt_roundpd_ps (6, xd, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC);
}
void extern
avx10_2_test_5 (void)
{
hxi = _mm256_cvt_roundpd_epi32 (xd, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
hxi = _mm256_mask_cvt_roundpd_epi32 (hxi, m8, xd, _MM_FROUND_TO_POS_INF | _MM_FROUND_NO_EXC);
hxi = _mm256_maskz_cvt_roundpd_epi32 (m8, xd, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC);
xi = _mm256_cvt_roundpd_epi64 (xd, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
xi = _mm256_mask_cvt_roundpd_epi64 (xi, m8, xd, _MM_FROUND_TO_POS_INF | _MM_FROUND_NO_EXC);
xi = _mm256_maskz_cvt_roundpd_epi64 (m8, xd, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC);
hxi = _mm256_cvt_roundpd_epu32 (xd, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
hxi = _mm256_mask_cvt_roundpd_epu32 (hxi, m8, xd, _MM_FROUND_TO_POS_INF | _MM_FROUND_NO_EXC);
hxi = _mm256_maskz_cvt_roundpd_epu32 (m8, xd, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC);
xi = _mm256_cvt_roundpd_epu64 (xd, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
xi = _mm256_mask_cvt_roundpd_epu64 (xi, m8, xd, _MM_FROUND_TO_NEG_INF | _MM_FROUND_NO_EXC);
xi = _mm256_maskz_cvt_roundpd_epu64 (m8, xd, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC);
}

4
gcc/testsuite/gcc.target/i386/sse-13.c
View file

@ -860,10 +860,6 @@
#define __builtin_ia32_cvtdq2ps256_mask_round(A, B, C, D) __builtin_ia32_cvtdq2ps256_mask_round(A, B, C, 8)
#define __builtin_ia32_vcvtpd2ph256_mask_round(A, B, C, D) __builtin_ia32_vcvtpd2ph256_mask_round(A, B, C, 8)
#define __builtin_ia32_cvtpd2ps256_mask_round(A, B, C, D) __builtin_ia32_cvtpd2ps256_mask_round(A, B, C, 8)
#define __builtin_ia32_cvtpd2dq256_mask_round(A, B, C, D) __builtin_ia32_cvtpd2dq256_mask_round(A, B, C, 8)
#define __builtin_ia32_cvtpd2qq256_mask_round(A, B, C, D) __builtin_ia32_cvtpd2qq256_mask_round(A, B, C, 8)
#define __builtin_ia32_cvtpd2udq256_mask_round(A, B, C, D) __builtin_ia32_cvtpd2udq256_mask_round(A, B, C, 8)
#define __builtin_ia32_cvtpd2uqq256_mask_round(A, B, C, D) __builtin_ia32_cvtpd2uqq256_mask_round(A, B, C, 8)
/* avx10_2-512mediaintrin.h */
#define __builtin_ia32_mpsadbw512(A, B, C) __builtin_ia32_mpsadbw512 (A, B, 1)

12
gcc/testsuite/gcc.target/i386/sse-14.c
View file

@ -1025,10 +1025,6 @@ test_1 (_mm256_cvt_roundepi32_ph, __m128h, __m256i, 8)
test_1 (_mm256_cvt_roundepi32_ps, __m256, __m256i, 9)
test_1 (_mm256_cvt_roundpd_ph, __m128h, __m256d, 8)
test_1 (_mm256_cvt_roundpd_ps, __m128, __m256d, 9)
test_1 (_mm256_cvt_roundpd_epi32, __m128i, __m256d, 9)
test_1 (_mm256_cvt_roundpd_epi64, __m256i, __m256d, 9)
test_1 (_mm256_cvt_roundpd_epu32, __m128i, __m256d, 9)
test_1 (_mm256_cvt_roundpd_epu64, __m256i, __m256d, 9)
test_2 (_mm256_add_round_pd, __m256d, __m256d, __m256d, 9)
test_2 (_mm256_add_round_ph, __m256h, __m256h, __m256h, 8)
test_2 (_mm256_add_round_ps, __m256, __m256, __m256, 9)
@ -1036,10 +1032,6 @@ test_2 (_mm256_maskz_cvt_roundepi32_ph, __m128h, __mmask8, __m256i, 8)
test_2 (_mm256_maskz_cvt_roundepi32_ps, __m256, __mmask8, __m256i, 9)
test_2 (_mm256_maskz_cvt_roundpd_ph, __m128h, __mmask8, __m256d, 8)
test_2 (_mm256_maskz_cvt_roundpd_ps, __m128, __mmask8, __m256d, 9)
test_2 (_mm256_maskz_cvt_roundpd_epi32, __m128i, __mmask8, __m256d, 9)
test_2 (_mm256_maskz_cvt_roundpd_epi64, __m256i, __mmask8, __m256d, 9)
test_2 (_mm256_maskz_cvt_roundpd_epu32, __m128i, __mmask8, __m256d, 9)
test_2 (_mm256_maskz_cvt_roundpd_epu64, __m256i, __mmask8, __m256d, 9)
test_2x (_mm256_cmp_round_pd_mask, __mmask8, __m256d, __m256d, 1, 8)
test_2x (_mm256_cmp_round_ph_mask, __mmask16, __m256h, __m256h, 1, 8)
test_2x (_mm256_cmp_round_ps_mask, __mmask8, __m256, __m256, 1, 8)
@ -1050,10 +1042,6 @@ test_3 (_mm256_mask_cvt_roundepi32_ph, __m128h, __m128h, __mmask8, __m256i, 8)
test_3 (_mm256_mask_cvt_roundepi32_ps, __m256, __m256, __mmask8, __m256i, 9)
test_3 (_mm256_mask_cvt_roundpd_ph, __m128h, __m128h, __mmask8, __m256d, 8)
test_3 (_mm256_mask_cvt_roundpd_ps, __m128, __m128, __mmask8, __m256d, 9)
test_3 (_mm256_mask_cvt_roundpd_epi32, __m128i, __m128i, __mmask8, __m256d, 9)
test_3 (_mm256_mask_cvt_roundpd_epu32, __m128i, __m128i, __mmask8, __m256d, 9)
test_3 (_mm256_mask_cvt_roundpd_epi64, __m256i, __m256i, __mmask8, __m256d, 9)
test_3 (_mm256_mask_cvt_roundpd_epu64, __m256i, __m256i, __mmask8, __m256d, 9)
test_3x (_mm256_mask_cmp_round_pd_mask, __mmask8, __mmask8, __m256d, __m256d, 1, 8)
test_3x (_mm256_mask_cmp_round_ph_mask, __mmask16, __mmask16, __m256h, __m256h, 1, 8)
test_3x (_mm256_mask_cmp_round_ps_mask, __mmask8, __mmask8, __m256, __m256, 1, 8)

12
gcc/testsuite/gcc.target/i386/sse-22.c
View file

@ -1066,10 +1066,6 @@ test_1 (_mm256_cvt_roundepi32_ph, __m128h, __m256i, 8)
test_1 (_mm256_cvt_roundepi32_ps, __m256, __m256i, 9)
test_1 (_mm256_cvt_roundpd_ph, __m128h, __m256d, 8)
test_1 (_mm256_cvt_roundpd_ps, __m128, __m256d, 9)
test_1 (_mm256_cvt_roundpd_epi32, __m128i, __m256d, 9)
test_1 (_mm256_cvt_roundpd_epi64, __m256i, __m256d, 9)
test_1 (_mm256_cvt_roundpd_epu32, __m128i, __m256d, 9)
test_1 (_mm256_cvt_roundpd_epu64, __m256i, __m256d, 9)
test_2 (_mm256_add_round_pd, __m256d, __m256d, __m256d, 9)
test_2 (_mm256_add_round_ph, __m256h, __m256h, __m256h, 8)
test_2 (_mm256_add_round_ps, __m256, __m256, __m256, 9)
@ -1077,10 +1073,6 @@ test_2 (_mm256_maskz_cvt_roundepi32_ph, __m128h, __mmask8, __m256i, 8)
test_2 (_mm256_maskz_cvt_roundepi32_ps, __m256, __mmask8, __m256i, 9)
test_2 (_mm256_maskz_cvt_roundpd_ph, __m128h, __mmask8, __m256d, 8)
test_2 (_mm256_maskz_cvt_roundpd_ps, __m128, __mmask8, __m256d, 9)
test_2 (_mm256_maskz_cvt_roundpd_epi32, __m128i, __mmask8, __m256d, 9)
test_2 (_mm256_maskz_cvt_roundpd_epi64, __m256i, __mmask8, __m256d, 9)
test_2 (_mm256_maskz_cvt_roundpd_epu32, __m128i, __mmask8, __m256d, 9)
test_2 (_mm256_maskz_cvt_roundpd_epu64, __m256i, __mmask8, __m256d, 9)
test_2x (_mm256_cmp_round_pd_mask, __mmask8, __m256d, __m256d, 1, 8)
test_2x (_mm256_cmp_round_ph_mask, __mmask16, __m256h, __m256h, 1, 8)
test_2x (_mm256_cmp_round_ps_mask, __mmask8, __m256, __m256, 1, 8)
@ -1091,10 +1083,6 @@ test_3 (_mm256_mask_cvt_roundepi32_ph, __m128h, __m128h, __mmask8, __m256i, 8)
test_3 (_mm256_mask_cvt_roundepi32_ps, __m256, __m256, __mmask8, __m256i, 9)
test_3 (_mm256_mask_cvt_roundpd_ph, __m128h, __m128h, __mmask8, __m256d, 8)
test_3 (_mm256_mask_cvt_roundpd_ps, __m128, __m128, __mmask8, __m256d, 9)
test_3 (_mm256_mask_cvt_roundpd_epi32, __m128i, __m128i, __mmask8, __m256d, 9)
test_3 (_mm256_mask_cvt_roundpd_epu32, __m128i, __m128i, __mmask8, __m256d, 9)
test_3 (_mm256_mask_cvt_roundpd_epi64, __m256i, __m256i, __mmask8, __m256d, 9)
test_3 (_mm256_mask_cvt_roundpd_epu64, __m256i, __m256i, __mmask8, __m256d, 9)
test_3x (_mm256_mask_cmp_round_pd_mask, __mmask8, __mmask8, __m256d, __m256d, 1, 8)
test_3x (_mm256_mask_cmp_round_ph_mask, __mmask16, __mmask16, __m256h, __m256h, 1, 8)
test_3x (_mm256_mask_cmp_round_ps_mask, __mmask8, __mmask8, __m256, __m256, 1, 8)

4
gcc/testsuite/gcc.target/i386/sse-23.c
View file

@ -835,10 +835,6 @@
#define __builtin_ia32_cvtdq2ps256_mask_round(A, B, C, D) __builtin_ia32_cvtdq2ps256_mask_round(A, B, C, 8)
#define __builtin_ia32_vcvtpd2ph256_mask_round(A, B, C, D) __builtin_ia32_vcvtpd2ph256_mask_round(A, B, C, 8)
#define __builtin_ia32_cvtpd2ps256_mask_round(A, B, C, D) __builtin_ia32_cvtpd2ps256_mask_round(A, B, C, 8)
#define __builtin_ia32_cvtpd2dq256_mask_round(A, B, C, D) __builtin_ia32_cvtpd2dq256_mask_round(A, B, C, 8)
#define __builtin_ia32_cvtpd2qq256_mask_round(A, B, C, D) __builtin_ia32_cvtpd2qq256_mask_round(A, B, C, 8)
#define __builtin_ia32_cvtpd2udq256_mask_round(A, B, C, D) __builtin_ia32_cvtpd2udq256_mask_round(A, B, C, 8)
#define __builtin_ia32_cvtpd2uqq256_mask_round(A, B, C, D) __builtin_ia32_cvtpd2uqq256_mask_round(A, B, C, 8)
/* avx10_2-512mediaintrin.h */
#define __builtin_ia32_mpsadbw512(A, B, C) __builtin_ia32_mpsadbw512 (A, B, 1)