RISC-V: Add Zalrsc amo-op patterns
All amo<op> patterns can be represented with lrsc sequences. Add these patterns as a fallback when Zaamo is not enabled. gcc/ChangeLog: * config/riscv/sync.md (atomic_<atomic_optab><mode>): New expand pattern. (amo_atomic_<atomic_optab><mode>): Rename amo pattern. (atomic_fetch_<atomic_optab><mode>): New lrsc sequence pattern. (lrsc_atomic_<atomic_optab><mode>): New expand pattern. (amo_atomic_fetch_<atomic_optab><mode>): Rename amo pattern. (lrsc_atomic_fetch_<atomic_optab><mode>): New lrsc sequence pattern. (atomic_exchange<mode>): New expand pattern. (amo_atomic_exchange<mode>): Rename amo pattern. (lrsc_atomic_exchange<mode>): New lrsc sequence pattern. gcc/testsuite/ChangeLog: * gcc.target/riscv/amo-zaamo-preferred-over-zalrsc.c: New test. * gcc.target/riscv/amo-zalrsc-amo-add-1.c: New test. * gcc.target/riscv/amo-zalrsc-amo-add-2.c: New test. * gcc.target/riscv/amo-zalrsc-amo-add-3.c: New test. * gcc.target/riscv/amo-zalrsc-amo-add-4.c: New test. * gcc.target/riscv/amo-zalrsc-amo-add-5.c: New test. Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
This commit is contained in:
Patrick O'Neill
parent
0fea902b1b
commit
1588983be6
7 changed files with 231 additions and 5 deletions
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@ -86,7 +86,24 @@
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DONE;
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})
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(define_insn "atomic_<atomic_optab><mode>"
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;; AMO ops
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(define_expand "atomic_<atomic_optab><mode>"
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[(any_atomic:GPR (match_operand:GPR 0 "memory_operand") ;; mem location
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(match_operand:GPR 1 "reg_or_0_operand")) ;; value for op
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(match_operand:SI 2 "const_int_operand")] ;; model
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"TARGET_ZAAMO || TARGET_ZALRSC"
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{
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if (TARGET_ZAAMO)
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emit_insn (gen_amo_atomic_<atomic_optab><mode> (operands[0], operands[1],
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operands[2]));
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else
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emit_insn (gen_lrsc_atomic_<atomic_optab><mode> (operands[0], operands[1],
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operands[2]));
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DONE;
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})
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(define_insn "amo_atomic_<atomic_optab><mode>"
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[(set (match_operand:GPR 0 "memory_operand" "+A")
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(unspec_volatile:GPR
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[(any_atomic:GPR (match_dup 0)
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@ -98,7 +115,44 @@
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[(set_attr "type" "atomic")
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(set (attr "length") (const_int 4))])
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(define_insn "atomic_fetch_<atomic_optab><mode>"
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(define_insn "lrsc_atomic_<atomic_optab><mode>"
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[(set (match_operand:GPR 0 "memory_operand" "+A")
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(unspec_volatile:GPR
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[(any_atomic:GPR (match_dup 0)
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(match_operand:GPR 1 "reg_or_0_operand" "rJ"))
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(match_operand:SI 2 "const_int_operand")] ;; model
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UNSPEC_SYNC_OLD_OP))
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(clobber (match_scratch:GPR 3 "=&r"))] ;; tmp_1
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"!TARGET_ZAAMO && TARGET_ZALRSC"
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{
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return "1:\;"
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"lr.<amo>%I2\t%3, %0\;"
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"<insn>\t%3, %3, %1\;"
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"sc.<amo>%J2\t%3, %3, %0\;"
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"bnez\t%3, 1b";
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}
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[(set_attr "type" "atomic")
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(set (attr "length") (const_int 16))])
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;; AMO fetch ops
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(define_expand "atomic_fetch_<atomic_optab><mode>"
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[(match_operand:GPR 0 "register_operand") ;; old value at mem
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(any_atomic:GPR (match_operand:GPR 1 "memory_operand") ;; mem location
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(match_operand:GPR 2 "reg_or_0_operand")) ;; value for op
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(match_operand:SI 3 "const_int_operand")] ;; model
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"TARGET_ZAAMO || TARGET_ZALRSC"
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{
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if (TARGET_ZAAMO)
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emit_insn (gen_amo_atomic_fetch_<atomic_optab><mode> (operands[0], operands[1],
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operands[2], operands[3]));
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else
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emit_insn (gen_lrsc_atomic_fetch_<atomic_optab><mode> (operands[0], operands[1],
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operands[2], operands[3]));
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DONE;
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})
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(define_insn "amo_atomic_fetch_<atomic_optab><mode>"
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[(set (match_operand:GPR 0 "register_operand" "=&r")
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(match_operand:GPR 1 "memory_operand" "+A"))
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(set (match_dup 1)
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@ -112,6 +166,27 @@
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[(set_attr "type" "atomic")
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(set (attr "length") (const_int 4))])
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(define_insn "lrsc_atomic_fetch_<atomic_optab><mode>"
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[(set (match_operand:GPR 0 "register_operand" "=&r")
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(match_operand:GPR 1 "memory_operand" "+A"))
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(set (match_dup 1)
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(unspec_volatile:GPR
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[(any_atomic:GPR (match_dup 1)
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(match_operand:GPR 2 "reg_or_0_operand" "rJ"))
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(match_operand:SI 3 "const_int_operand")] ;; model
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UNSPEC_SYNC_OLD_OP))
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(clobber (match_scratch:GPR 4 "=&r"))] ;; tmp_1
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"!TARGET_ZAAMO && TARGET_ZALRSC"
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{
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return "1:\;"
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"lr.<amo>%I3\t%0, %1\;"
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"<insn>\t%4, %0, %2\;"
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"sc.<amo>%J3\t%4, %4, %1\;"
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"bnez\t%4, 1b";
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}
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[(set_attr "type" "atomic")
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(set (attr "length") (const_int 20))])
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(define_insn "subword_atomic_fetch_strong_<atomic_optab>"
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[(set (match_operand:SI 0 "register_operand" "=&r") ;; old value at mem
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(match_operand:SI 1 "memory_operand" "+A")) ;; mem location
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@ -248,7 +323,23 @@
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DONE;
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})
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(define_insn "atomic_exchange<mode>"
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(define_expand "atomic_exchange<mode>"
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[(match_operand:GPR 0 "register_operand") ;; old value at mem
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(match_operand:GPR 1 "memory_operand") ;; mem location
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(match_operand:GPR 2 "register_operand") ;; value for op
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(match_operand:SI 3 "const_int_operand")] ;; model
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"TARGET_ZAAMO || TARGET_ZALRSC"
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{
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if (TARGET_ZAAMO)
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emit_insn (gen_amo_atomic_exchange<mode> (operands[0], operands[1],
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operands[2], operands[3]));
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else
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emit_insn (gen_lrsc_atomic_exchange<mode> (operands[0], operands[1],
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operands[2], operands[3]));
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DONE;
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})
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(define_insn "amo_atomic_exchange<mode>"
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[(set (match_operand:GPR 0 "register_operand" "=&r")
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(unspec_volatile:GPR
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[(match_operand:GPR 1 "memory_operand" "+A")
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@ -261,6 +352,26 @@
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[(set_attr "type" "atomic")
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(set (attr "length") (const_int 4))])
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(define_insn "lrsc_atomic_exchange<mode>"
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[(set (match_operand:GPR 0 "register_operand" "=&r")
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(unspec_volatile:GPR
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[(match_operand:GPR 1 "memory_operand" "+A")
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(match_operand:SI 3 "const_int_operand")] ;; model
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UNSPEC_SYNC_EXCHANGE))
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(set (match_dup 1)
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(match_operand:GPR 2 "register_operand" "0"))
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(clobber (match_scratch:GPR 4 "=&r"))] ;; tmp_1
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"!TARGET_ZAAMO && TARGET_ZALRSC"
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{
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return "1:\;"
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"lr.<amo>%I3\t%4, %1\;"
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"sc.<amo>%J3\t%0, %0, %1\;"
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"bnez\t%0, 1b\;"
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"mv\t%0, %4";
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}
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[(set_attr "type" "atomic")
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(set (attr "length") (const_int 20))])
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(define_expand "atomic_exchange<mode>"
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[(match_operand:SHORT 0 "register_operand") ;; old value at mem
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(match_operand:SHORT 1 "memory_operand") ;; mem location
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@ -516,7 +627,7 @@
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[(match_operand:QI 0 "register_operand" "") ;; bool output
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(match_operand:QI 1 "memory_operand" "+A") ;; memory
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(match_operand:SI 2 "const_int_operand" "")] ;; model
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"TARGET_ZALRSC"
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"TARGET_ZAAMO || TARGET_ZALRSC"
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{
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/* We have no QImode atomics, so use the address LSBs to form a mask,
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then use an aligned SImode atomic. */
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@ -537,7 +648,10 @@
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rtx shifted_set = gen_reg_rtx (SImode);
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riscv_lshift_subword (QImode, set, shift, &shifted_set);
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emit_insn (gen_atomic_fetch_orsi (old, aligned_mem, shifted_set, model));
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if (TARGET_ZAAMO)
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emit_insn (gen_amo_atomic_fetch_orsi (old, aligned_mem, shifted_set, model));
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else if (TARGET_ZALRSC)
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emit_insn (gen_lrsc_atomic_fetch_orsi (old, aligned_mem, shifted_set, model));
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emit_move_insn (old, gen_rtx_ASHIFTRT (SImode, old,
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gen_lowpart (QImode, shift)));
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@ -0,0 +1,17 @@
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/* { dg-do compile } */
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/* Ensure that AMO ops are emitted when both zalrsc and zaamo are enabled. */
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/* { dg-options "-O3" } */
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/* { dg-add-options riscv_zalrsc } */
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/* { dg-add-options riscv_zaamo } */
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/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
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/* { dg-final { check-function-bodies "**" "" } } */
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/*
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** foo:
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** amoadd\.w\tzero,a1,0\(a0\)
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** ret
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*/
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void foo (int* bar, int* baz)
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{
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__atomic_add_fetch(bar, baz, __ATOMIC_RELAXED);
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}
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19
gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-1.c
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19
gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-1.c
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@ -0,0 +1,19 @@
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/* { dg-do compile } */
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/* Verify that lrsc atomic op mappings match Table A.6's recommended mapping. */
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/* { dg-options "-O3 -march=rv64id_zalrsc -mabi=lp64d" } */
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/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
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/* { dg-final { check-function-bodies "**" "" } } */
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/*
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** foo:
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** 1:
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** lr.w\t[atx][0-9]+, 0\(a0\)
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** add\t[atx][0-9]+, [atx][0-9]+, a1
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** sc.w\t[atx][0-9]+, [atx][0-9]+, 0\(a0\)
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** bnez\t[atx][0-9]+, 1b
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** ret
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*/
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void foo (int* bar, int* baz)
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{
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__atomic_add_fetch(bar, baz, __ATOMIC_RELAXED);
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}
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19
gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-2.c
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19
gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-2.c
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@ -0,0 +1,19 @@
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/* { dg-do compile } */
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/* Verify that lrsc atomic op mappings match Table A.6's recommended mapping. */
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/* { dg-options "-O3 -march=rv64id_zalrsc -mabi=lp64d" } */
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/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
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/* { dg-final { check-function-bodies "**" "" } } */
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/*
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** foo:
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** 1:
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** lr.w.aq\t[atx][0-9]+, 0\(a0\)
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** add\t[atx][0-9]+, [atx][0-9]+, a1
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** sc.w\t[atx][0-9]+, [atx][0-9]+, 0\(a0\)
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** bnez\t[atx][0-9]+, 1b
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** ret
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*/
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void foo (int* bar, int* baz)
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{
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__atomic_add_fetch(bar, baz, __ATOMIC_ACQUIRE);
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}
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19
gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-3.c
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19
gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-3.c
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@ -0,0 +1,19 @@
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/* { dg-do compile } */
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/* Verify that lrsc atomic op mappings match Table A.6's recommended mapping. */
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/* { dg-options "-O3 -march=rv64id_zalrsc -mabi=lp64d" } */
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/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
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/* { dg-final { check-function-bodies "**" "" } } */
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/*
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** foo:
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** 1:
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** lr.w\t[atx][0-9]+, 0\(a0\)
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** add\t[atx][0-9]+, [atx][0-9]+, a1
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** sc.w.rl\t[atx][0-9]+, [atx][0-9]+, 0\(a0\)
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** bnez\t[atx][0-9]+, 1b
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** ret
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*/
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void foo (int* bar, int* baz)
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{
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__atomic_add_fetch(bar, baz, __ATOMIC_RELEASE);
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}
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19
gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-4.c
Normal file
19
gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-4.c
Normal file
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@ -0,0 +1,19 @@
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/* { dg-do compile } */
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/* Verify that lrsc atomic op mappings match Table A.6's recommended mapping. */
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/* { dg-options "-O3 -march=rv64id_zalrsc -mabi=lp64d" } */
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/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
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/* { dg-final { check-function-bodies "**" "" } } */
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/*
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** foo:
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** 1:
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** lr.w.aq\t[atx][0-9]+, 0\(a0\)
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** add\t[atx][0-9]+, [atx][0-9]+, a1
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** sc.w.rl\t[atx][0-9]+, [atx][0-9]+, 0\(a0\)
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** bnez\t[atx][0-9]+, 1b
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** ret
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*/
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void foo (int* bar, int* baz)
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{
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__atomic_add_fetch(bar, baz, __ATOMIC_ACQ_REL);
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}
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19
gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-5.c
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19
gcc/testsuite/gcc.target/riscv/amo-zalrsc-amo-add-5.c
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@ -0,0 +1,19 @@
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/* { dg-do compile } */
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/* Verify that lrsc atomic op mappings match Table A.6's recommended mapping. */
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/* { dg-options "-O3 -march=rv64id_zalrsc -mabi=lp64d" } */
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/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
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/* { dg-final { check-function-bodies "**" "" } } */
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/*
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** foo:
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** 1:
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** lr.w.aqrl\t[atx][0-9]+, 0\(a0\)
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** add\t[atx][0-9]+, [atx][0-9]+, a1
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** sc.w.rl\t[atx][0-9]+, [atx][0-9]+, 0\(a0\)
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** bnez\t[atx][0-9]+, 1b
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** ret
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*/
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void foo (int* bar, int* baz)
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{
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__atomic_add_fetch(bar, baz, __ATOMIC_SEQ_CST);
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}
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