RISC-V: Add Zalrsc and Zaamo testsuite support

Convert testsuite infrastructure to use Zalrsc and Zaamo rather than A.

gcc/ChangeLog:

	* doc/sourcebuild.texi: Add docs for atomic extension testsuite infra.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/amo-table-a-6-amo-add-1.c: Use Zaamo rather than A.
	* gcc.target/riscv/amo-table-a-6-amo-add-2.c: Ditto.
	* gcc.target/riscv/amo-table-a-6-amo-add-3.c: Ditto.
	* gcc.target/riscv/amo-table-a-6-amo-add-4.c: Ditto.
	* gcc.target/riscv/amo-table-a-6-amo-add-5.c: Ditto.
	* gcc.target/riscv/amo-table-a-6-compare-exchange-1.c: Use Zalrsc rather
	than A.
	* gcc.target/riscv/amo-table-a-6-compare-exchange-2.c: Ditto.
	* gcc.target/riscv/amo-table-a-6-compare-exchange-3.c: Ditto.
	* gcc.target/riscv/amo-table-a-6-compare-exchange-4.c: Ditto.
	* gcc.target/riscv/amo-table-a-6-compare-exchange-5.c: Ditto.
	* gcc.target/riscv/amo-table-a-6-compare-exchange-6.c: Ditto.
	* gcc.target/riscv/amo-table-a-6-compare-exchange-7.c: Ditto.
	* gcc.target/riscv/amo-table-a-6-subword-amo-add-1.c: Use Zaamo rather
	than A.
	* gcc.target/riscv/amo-table-a-6-subword-amo-add-2.c: Ditto.
	* gcc.target/riscv/amo-table-a-6-subword-amo-add-3.c: Ditto.
	* gcc.target/riscv/amo-table-a-6-subword-amo-add-4.c: Ditto.
	* gcc.target/riscv/amo-table-a-6-subword-amo-add-5.c: Ditto.
	* gcc.target/riscv/amo-table-ztso-amo-add-1.c: Add Zaamo option.
	* gcc.target/riscv/amo-table-ztso-amo-add-2.c: Ditto.
	* gcc.target/riscv/amo-table-ztso-amo-add-3.c: Ditto.
	* gcc.target/riscv/amo-table-ztso-amo-add-4.c: Ditto.
	* gcc.target/riscv/amo-table-ztso-amo-add-5.c: Ditto.
	* gcc.target/riscv/amo-table-ztso-compare-exchange-1.c: Use Zalrsc rather
	than A.
	* gcc.target/riscv/amo-table-ztso-compare-exchange-2.c: Ditto.
	* gcc.target/riscv/amo-table-ztso-compare-exchange-3.c: Ditto.
	* gcc.target/riscv/amo-table-ztso-compare-exchange-4.c: Ditto.
	* gcc.target/riscv/amo-table-ztso-compare-exchange-5.c: Ditto.
	* gcc.target/riscv/amo-table-ztso-compare-exchange-6.c: Ditto.
	* gcc.target/riscv/amo-table-ztso-compare-exchange-7.c: Ditto.
	* gcc.target/riscv/amo-table-ztso-subword-amo-add-1.c: Ditto.
	* gcc.target/riscv/amo-table-ztso-subword-amo-add-2.c: Ditto.
	* gcc.target/riscv/amo-table-ztso-subword-amo-add-3.c: Ditto.
	* gcc.target/riscv/amo-table-ztso-subword-amo-add-4.c: Ditto.
	* gcc.target/riscv/amo-table-ztso-subword-amo-add-5.c: Ditto.
	* lib/target-supports.exp: Add testsuite infrastructure support for
	Zaamo and Zalrsc.

Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>

gcc/doc/sourcebuild.texi

@@ -2513,8 +2513,17 @@ Test system has an integer register width of 32 bits.
 @item rv64
 Test system has an integer register width of 64 bits.
 
-@item cv_bi
-Test system has support for the CORE-V BI extension.
+@item riscv_a
+Test target architecture has support for the A extension.
+
+@item riscv_zaamo
+Test target architecture has support for the zaamo extension.
+
+@item riscv_zlrsc
+Test target architecture has support for the zalrsc extension.
+
+@item riscv_ztso
+Test target architecture has support for the ztso extension.
 
 @end table
 
@@ -2534,6 +2543,9 @@ Test system has support for the CORE-V ELW extension.
 @item cv_simd
 Test system has support for the CORE-V SIMD extension.
 
+@item cv_bi
+Test system has support for the CORE-V BI extension.
+
 @end table
 
 @subsubsection Other hardware attributes

gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-1.c

@@ -1,7 +1,7 @@
 /* { dg-do compile } */
 /* Verify that atomic op mappings match Table A.6's recommended mapping.  */
 /* { dg-options "-O3" } */
-/* { dg-add-options riscv_a } */
+/* { dg-add-options riscv_zaamo } */
 /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
 /* { dg-final { check-function-bodies "**" "" } } */
 

gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-2.c

@@ -1,7 +1,7 @@
 /* { dg-do compile } */
 /* Verify that atomic op mappings match Table A.6's recommended mapping.  */
 /* { dg-options "-O3" } */
-/* { dg-add-options riscv_a } */
+/* { dg-add-options riscv_zaamo } */
 /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
 /* { dg-final { check-function-bodies "**" "" } } */
 

gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-3.c

@@ -1,7 +1,7 @@
 /* { dg-do compile } */
 /* Verify that atomic op mappings match Table A.6's recommended mapping.  */
 /* { dg-options "-O3" } */
-/* { dg-add-options riscv_a } */
+/* { dg-add-options riscv_zaamo } */
 /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
 /* { dg-final { check-function-bodies "**" "" } } */
 

gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-4.c

@@ -1,7 +1,7 @@
 /* { dg-do compile } */
 /* Verify that atomic op mappings match Table A.6's recommended mapping.  */
 /* { dg-options "-O3" } */
-/* { dg-add-options riscv_a } */
+/* { dg-add-options riscv_zaamo } */
 /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
 /* { dg-final { check-function-bodies "**" "" } } */
 

gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-5.c

@@ -1,7 +1,7 @@
 /* { dg-do compile } */
 /* Verify that atomic op mappings match Table A.6's recommended mapping.  */
 /* { dg-options "-O3" } */
-/* { dg-add-options riscv_a } */
+/* { dg-add-options riscv_zaamo } */
 /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
 /* { dg-final { check-function-bodies "**" "" } } */
 

gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-1.c

@@ -1,6 +1,6 @@
 /* { dg-do compile } */
 /* Verify that compare exchange mappings match Table A.6's recommended mapping.  */
-/* { dg-add-options riscv_a } */
+/* { dg-add-options riscv_zalrsc } */
 /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */
 

gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-2.c

@@ -1,6 +1,6 @@
 /* { dg-do compile } */
 /* Verify that compare exchange mappings match Table A.6's recommended mapping.  */
-/* { dg-add-options riscv_a } */
+/* { dg-add-options riscv_zalrsc } */
 /* { dg-final { scan-assembler-times "lr.w.aq\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */
 

gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-3.c

@@ -1,6 +1,6 @@
 /* { dg-do compile } */
 /* Verify that compare exchange mappings match Table A.6's recommended mapping.  */
-/* { dg-add-options riscv_a } */
+/* { dg-add-options riscv_zalrsc } */
 /* { dg-final { scan-assembler-times "lr.w.aq\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */
 

gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-4.c

@@ -1,6 +1,6 @@
 /* { dg-do compile } */
 /* Verify that compare exchange mappings match Table A.6's recommended mapping.  */
-/* { dg-add-options riscv_a } */
+/* { dg-add-options riscv_zalrsc } */
 /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */
 

gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-5.c

@@ -1,6 +1,6 @@
 /* { dg-do compile } */
 /* Verify that compare exchange mappings match Table A.6's recommended mapping.  */
-/* { dg-add-options riscv_a } */
+/* { dg-add-options riscv_zalrsc } */
 /* { dg-final { scan-assembler-times "lr.w.aqrl\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */
 

gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-6.c

@@ -1,6 +1,6 @@
 /* { dg-do compile } */
 /* Verify that compare exchange mappings match Table A.6's recommended mapping.  */
-/* { dg-add-options riscv_a } */
+/* { dg-add-options riscv_zalrsc } */
 /* Mixed mappings need to be unioned.  */
 /* { dg-final { scan-assembler-times "lr.w.aq\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */

gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-7.c

@@ -1,6 +1,6 @@
 /* { dg-do compile } */
 /* Verify that compare exchange mappings match Table A.6's recommended mapping.  */
-/* { dg-add-options riscv_a } */
+/* { dg-add-options riscv_zalrsc } */
 /* { dg-final { scan-assembler-times "lr.w.aqrl\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */
 

gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-1.c

@@ -1,6 +1,6 @@
 /* { dg-do compile } */
 /* Verify that subword atomic op mappings match Table A.6's recommended mapping.  */
-/* { dg-add-options riscv_a } */
+/* { dg-add-options riscv_zalrsc } */
 /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */
 

gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-2.c

@@ -1,6 +1,6 @@
 /* { dg-do compile } */
 /* Verify that subword atomic op mappings match Table A.6's recommended mapping.  */
-/* { dg-add-options riscv_a } */
+/* { dg-add-options riscv_zalrsc } */
 /* { dg-final { scan-assembler-times "lr.w.aq\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */
 

gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-3.c

@@ -1,6 +1,6 @@
 /* { dg-do compile } */
 /* Verify that subword atomic op mappings match Table A.6's recommended mapping.  */
-/* { dg-add-options riscv_a } */
+/* { dg-add-options riscv_zalrsc } */
 /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */
 

gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-4.c

@@ -1,6 +1,6 @@
 /* { dg-do compile } */
 /* Verify that subword atomic op mappings match Table A.6's recommended mapping.  */
-/* { dg-add-options riscv_a } */
+/* { dg-add-options riscv_zalrsc } */
 /* { dg-final { scan-assembler-times "lr.w.aq\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */
 

gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-5.c

@@ -1,6 +1,6 @@
 /* { dg-do compile } */
 /* Verify that subword atomic op mappings match Table A.6's recommended mapping.  */
-/* { dg-add-options riscv_a } */
+/* { dg-add-options riscv_zalrsc } */
 /* { dg-final { scan-assembler-times "lr.w.aqrl\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */
 

gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-1.c

@@ -1,7 +1,7 @@
 /* { dg-do compile } */
 /* Verify that atomic op mappings match the Ztso suggested mapping.  */
 /* { dg-options "-O3" } */
-/* { dg-add-options riscv_a } */
+/* { dg-add-options riscv_zaamo } */
 /* { dg-add-options riscv_ztso } */
 /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
 /* { dg-final { check-function-bodies "**" "" } } */

gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-2.c

@@ -1,7 +1,7 @@
 /* { dg-do compile } */
 /* Verify that atomic op mappings the Ztso suggested mapping.  */
 /* { dg-options "-O3" } */
-/* { dg-add-options riscv_a } */
+/* { dg-add-options riscv_zaamo } */
 /* { dg-add-options riscv_ztso } */
 /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
 /* { dg-final { check-function-bodies "**" "" } } */

gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-3.c

@@ -1,7 +1,7 @@
 /* { dg-do compile } */
 /* Verify that atomic op mappings match the Ztso suggested mapping.  */
 /* { dg-options "-O3" } */
-/* { dg-add-options riscv_a } */
+/* { dg-add-options riscv_zaamo } */
 /* { dg-add-options riscv_ztso } */
 /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
 /* { dg-final { check-function-bodies "**" "" } } */

gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-4.c

@@ -1,7 +1,7 @@
 /* { dg-do compile } */
 /* Verify that atomic op mappings match the Ztso suggested mapping.  */
 /* { dg-options "-O3" } */
-/* { dg-add-options riscv_a } */
+/* { dg-add-options riscv_zaamo } */
 /* { dg-add-options riscv_ztso } */
 /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
 /* { dg-final { check-function-bodies "**" "" } } */

gcc/testsuite/gcc.target/riscv/amo-table-ztso-amo-add-5.c

@@ -1,7 +1,7 @@
 /* { dg-do compile } */
 /* Verify that atomic op mappings match the Ztso suggested mapping.  */
 /* { dg-options "-O3" } */
-/* { dg-add-options riscv_a } */
+/* { dg-add-options riscv_zaamo } */
 /* { dg-add-options riscv_ztso } */
 /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
 /* { dg-final { check-function-bodies "**" "" } } */

gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-1.c

@@ -1,6 +1,6 @@
 /* { dg-do compile } */
 /* Verify that compare exchange mappings match the Ztso suggested mapping.  */
-/* { dg-add-options riscv_a } */
+/* { dg-add-options riscv_zalrsc } */
 /* { dg-add-options riscv_ztso } */
 /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */

gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-2.c

@@ -1,6 +1,6 @@
 /* { dg-do compile } */
 /* Verify that compare exchange mappings match the Ztso suggested mapping.  */
-/* { dg-add-options riscv_a } */
+/* { dg-add-options riscv_zalrsc } */
 /* { dg-add-options riscv_ztso } */
 /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */

gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-3.c

@@ -1,6 +1,6 @@
 /* { dg-do compile } */
 /* Verify that compare exchange mappings match the Ztso suggested mapping.  */
-/* { dg-add-options riscv_a } */
+/* { dg-add-options riscv_zalrsc } */
 /* { dg-add-options riscv_ztso } */
 /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */

gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-4.c

@@ -1,6 +1,6 @@
 /* { dg-do compile } */
 /* Verify that compare exchange mappings match the Ztso suggested mapping.  */
-/* { dg-add-options riscv_a } */
+/* { dg-add-options riscv_zalrsc } */
 /* { dg-add-options riscv_ztso } */
 /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */

gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-5.c

@@ -1,6 +1,6 @@
 /* { dg-do compile } */
 /* Verify that compare exchange mappings match the Ztso suggested mapping.  */
-/* { dg-add-options riscv_a } */
+/* { dg-add-options riscv_zalrsc } */
 /* { dg-add-options riscv_ztso } */
 /* { dg-final { scan-assembler-times "lr.w.aqrl\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */

gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-6.c

@@ -1,6 +1,6 @@
 /* { dg-do compile } */
 /* Verify that compare exchange mappings match the Ztso suggested mapping.  */
-/* { dg-add-options riscv_a } */
+/* { dg-add-options riscv_zalrsc } */
 /* { dg-add-options riscv_ztso } */
 /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */

gcc/testsuite/gcc.target/riscv/amo-table-ztso-compare-exchange-7.c

@@ -1,6 +1,6 @@
 /* { dg-do compile } */
 /* Verify that compare exchange mappings match the Ztso suggested mapping.  */
-/* { dg-add-options riscv_a } */
+/* { dg-add-options riscv_zalrsc } */
 /* { dg-add-options riscv_ztso } */
 /* { dg-final { scan-assembler-times "lr.w.aqrl\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */

gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-1.c

@@ -1,6 +1,6 @@
 /* { dg-do compile } */
 /* Verify that subword atomic op mappings match the Ztso suggested mapping.  */
-/* { dg-add-options riscv_a } */
+/* { dg-add-options riscv_zalrsc } */
 /* { dg-add-options riscv_ztso } */
 /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */

gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-2.c

@@ -1,6 +1,6 @@
 /* { dg-do compile } */
 /* Verify that subword atomic op mappings match the Ztso suggested mapping.  */
-/* { dg-add-options riscv_a } */
+/* { dg-add-options riscv_zalrsc } */
 /* { dg-add-options riscv_ztso } */
 /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */

gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-3.c

@@ -1,6 +1,6 @@
 /* { dg-do compile } */
 /* Verify that subword atomic op mappings match the Ztso suggested mapping.  */
-/* { dg-add-options riscv_a } */
+/* { dg-add-options riscv_zalrsc } */
 /* { dg-add-options riscv_ztso } */
 /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */

gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-4.c

@@ -1,6 +1,6 @@
 /* { dg-do compile } */
 /* Verify that subword atomic op mappings match the Ztso suggested mapping.  */
-/* { dg-add-options riscv_a } */
+/* { dg-add-options riscv_zalrsc } */
 /* { dg-add-options riscv_ztso } */
 /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */

gcc/testsuite/gcc.target/riscv/amo-table-ztso-subword-amo-add-5.c

@@ -1,6 +1,6 @@
 /* { dg-do compile } */
 /* Verify that subword atomic op mappings match the Ztso suggested mapping.  */
-/* { dg-add-options riscv_a } */
+/* { dg-add-options riscv_zalrsc } */
 /* { dg-add-options riscv_ztso } */
 /* { dg-final { scan-assembler-times "lr.w.aqrl\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */

gcc/testsuite/lib/target-supports.exp

@@ -1889,6 +1889,28 @@ proc check_effective_target_riscv_a { } {
     }]
 }
 
+# Return 1 if the target arch supports the atomic LRSC extension, 0 otherwise.
+# Cache the result.
+
+proc check_effective_target_riscv_zalrsc { } {
+    return [check_no_compiler_messages riscv_ext_zalrsc assembly {
+       #ifndef __riscv_zalrsc
+       #error "Not __riscv_zalrsc"
+       #endif
+    }]
+}
+
+# Return 1 if the target arch supports the atomic AMO extension, 0 otherwise.
+# Cache the result.
+
+proc check_effective_target_riscv_zaamo { } {
+    return [check_no_compiler_messages riscv_ext_zaamo assembly {
+       #ifndef __riscv_zaamo
+       #error "Not __riscv_zaamo"
+       #endif
+    }]
+}
+
 # Return 1 if the target arch supports the double precision floating point
 # extension, 0 otherwise.  Cache the result.
 
@@ -2107,7 +2129,7 @@ proc check_effective_target_riscv_v_misalign_ok { } {
 proc riscv_get_arch { } {
     set gcc_march ""
     # ??? do we neeed to add more extensions to the list below?
-    foreach ext { i m a f d q c v zicsr zifencei zfh zba zbb zbc zbs zvbb zvfh ztso } {
+    foreach ext { i m a f d q c v zicsr zifencei zfh zba zbb zbc zbs zvbb zvfh ztso zaamo zalrsc } {
 	if { [check_no_compiler_messages  riscv_ext_$ext assembly [string map [list DEF __riscv_$ext] {
 		#ifndef DEF
 		#error "Not DEF"
@@ -2166,6 +2188,30 @@ proc add_options_for_riscv_v { flags } {
     return "$flags -march=[regsub {[[:alnum:]]*} [riscv_get_arch] &v]"
 }
 
+proc add_options_for_riscv_zaamo { flags } {
+    if { [lsearch $flags -march=*] >= 0 } {
+	# If there are multiple -march flags, we have to adjust all of them.
+	set flags [regsub -all -- {(?:^|[[:space:]])-march=[[:alnum:]_.]*} $flags &_zaamo ]
+	return [regsub -all -- {((?:^|[[:space:]])-march=[[:alnum:]_.]*_zaamo[[:alnum:]_.]*)_zaamo} $flags \\1 ]
+    }
+    if { [check_effective_target_riscv_zaamo] } {
+	return "$flags"
+    }
+    return "$flags -march=[riscv_get_arch]_zaamo"
+}
+
+proc add_options_for_riscv_zalrsc { flags } {
+    if { [lsearch $flags -march=*] >= 0 } {
+	# If there are multiple -march flags, we have to adjust all of them.
+	set flags [regsub -all -- {(?:^|[[:space:]])-march=[[:alnum:]_.]*} $flags &_zalrsc ]
+	return [regsub -all -- {((?:^|[[:space:]])-march=[[:alnum:]_.]*_zalrsc[[:alnum:]_.]*)_zalrsc} $flags \\1 ]
+    }
+    if { [check_effective_target_riscv_zalrsc] } {
+	return "$flags"
+    }
+    return "$flags -march=[riscv_get_arch]_zalrsc"
+}
+
 proc add_options_for_riscv_zfh { flags } {
     if { [lsearch $flags -march=*] >= 0 } {
 	# If there are multiple -march flags, we have to adjust all of them.