cf5180a955
This checkin completes what is required to actually generate SSE5 instructions. No support in the disassembler yet. This checkin covers: - Support for actually generating DREX prefixes. - Support for matching operand "operand X must match Y"
16 lines
482 B
NASM
16 lines
482 B
NASM
bits 64
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fmsubps xmm0,xmm0,xmm1,xmm2
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fmsubps xmm0,xmm0,xmm1,[rax]
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fmsubps xmm0,xmm0,xmm1,[rax+0x77]
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fmsubps xmm0,xmm0,xmm1,[rax+0x7777]
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fmsubps xmm1,xmm2,xmm3,xmm1
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fmsubps xmm1,xmm2,[rax],xmm1
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fmsubps xmm1,xmm2,[rax+0x77],xmm1
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fmsubps xmm1,xmm2,[rax+0x7777],xmm1
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fmsubps xmm0,[rax],xmm2,xmm0
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fmsubps xmm0,[rax+0x77],xmm2,xmm0
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fmsubps xmm0,[rax+0x7777],xmm2,xmm0
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fmsubps xmm14,[rax],xmm2,xmm14
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fmsubps xmm14,[rax+0x77],xmm2,xmm14
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fmsubps xmm14,[rax+0x7777],xmm2,xmm14
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