dcaef4b095
* http://www.intel.com/software/isa * Signed-off-by: Mark Charney <mark.charney@intel.com>
254 lines
9.9 KiB
Perl
254 lines
9.9 KiB
Perl
#!/usr/bin/perl
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## --------------------------------------------------------------------------
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##
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## Copyright 1996-2013 The NASM Authors - All Rights Reserved
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## See the file AUTHORS included with the NASM distribution for
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## the specific copyright holders.
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##
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## Redistribution and use in source and binary forms, with or without
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## modification, are permitted provided that the following
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## conditions are met:
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##
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## * Redistributions of source code must retain the above copyright
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## notice, this list of conditions and the following disclaimer.
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## * Redistributions in binary form must reproduce the above
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## copyright notice, this list of conditions and the following
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## disclaimer in the documentation and/or other materials provided
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## with the distribution.
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##
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## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
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## CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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## INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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## MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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## DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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## CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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## SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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## NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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## LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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## HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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## OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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## EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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##
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## --------------------------------------------------------------------------
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#
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# Instruction template flags. These specify which processor
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# targets the instruction is eligible for, whether it is
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# privileged or undocumented, and also specify extra error
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# checking on the matching of the instruction.
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#
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# IF_SM stands for Size Match: any operand whose size is not
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# explicitly specified by the template is `really' intended to be
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# the same size as the first size-specified operand.
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# Non-specification is tolerated in the input instruction, but
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# _wrong_ specification is not.
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#
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# IF_SM2 invokes Size Match on only the first _two_ operands, for
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# three-operand instructions such as SHLD: it implies that the
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# first two operands must match in size, but that the third is
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# required to be _unspecified_.
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#
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# IF_SB invokes Size Byte: operands with unspecified size in the
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# template are really bytes, and so no non-byte specification in
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# the input instruction will be tolerated. IF_SW similarly invokes
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# Size Word, and IF_SD invokes Size Doubleword.
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#
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# (The default state if neither IF_SM nor IF_SM2 is specified is
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# that any operand with unspecified size in the template is
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# required to have unspecified size in the instruction too...)
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#
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# iflag_t is defined to store these flags.
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#
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# The order does matter here. We use some predefined masks to quick test
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# for a set of flags, so be careful moving bits (and
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# don't forget to update C code generation then).
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#
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my %insns_flag_bit = (
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#
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# dword bound, index 0 - specific flags
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#
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"SM" => [ 0, "Size match"],
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"SM2" => [ 1, "Size match first two operands"],
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"SB" => [ 2, "Unsized operands can't be non-byte"],
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"SW" => [ 3, "Unsized operands can't be non-word"],
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"SD" => [ 4, "Unsized operands can't be non-dword"],
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"SQ" => [ 5, "Unsized operands can't be non-qword"],
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"SO" => [ 6, "Unsized operands can't be non-oword"],
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"SY" => [ 7, "Unsized operands can't be non-yword"],
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"SZ" => [ 8, "Unsized operands can't be non-zword"],
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"SIZE" => [ 9, "Unsized operands must match the bitsize"],
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"SX" => [ 10, "Unsized operands not allowed"],
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"AR0" => [ 11, "SB, SW, SD applies to argument 0"],
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"AR1" => [ 12, "SB, SW, SD applies to argument 1"],
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"AR2" => [ 13, "SB, SW, SD applies to argument 2"],
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"AR3" => [ 14, "SB, SW, SD applies to argument 3"],
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"AR4" => [ 15, "SB, SW, SD applies to argument 4"],
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"OPT" => [ 16, "Optimizing assembly only"],
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#
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# dword bound, index 1 - instruction filtering flags
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#
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"PRIV" => [ 32, "Privileged instruction"],
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"SMM" => [ 33, "Only valid in SMM"],
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"PROT" => [ 34, "Protected mode only"],
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"LOCK" => [ 35, "Lockable if operand 0 is memory"],
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"NOLONG" => [ 36, "Not available in long mode"],
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"LONG" => [ 37, "Long mode"],
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"NOHLE" => [ 38, "HLE prefixes forbidden"],
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"MIB" => [ 39, "disassemble with split EA"],
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"BND" => [ 40, "BND (0xF2) prefix available"],
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"UNDOC" => [ 41, "Undocumented"],
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"HLE" => [ 42, "HLE prefixed"],
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"FPU" => [ 43, "FPU"],
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"MMX" => [ 44, "MMX"],
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"3DNOW" => [ 45, "3DNow!"],
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"SSE" => [ 46, "SSE (KNI, MMX2)"],
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"SSE2" => [ 47, "SSE2"],
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"SSE3" => [ 48, "SSE3 (PNI)"],
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"VMX" => [ 49, "VMX"],
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"SSSE3" => [ 50, "SSSE3"],
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"SSE4A" => [ 51, "AMD SSE4a"],
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"SSE41" => [ 52, "SSE4.1"],
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"SSE42" => [ 53, "SSE4.2"],
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"SSE5" => [ 54, "SSE5"],
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"AVX" => [ 55, "AVX (128b)"],
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"AVX2" => [ 56, "AVX2 (256b)"],
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"FMA" => [ 57, ""],
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"BMI1" => [ 58, ""],
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"BMI2" => [ 59, ""],
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"TBM" => [ 60, ""],
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"RTM" => [ 61, ""],
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"INVPCID" => [ 62, ""],
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#
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# dword bound, index 2 - instruction filtering flags
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#
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"AVX512" => [ 64, "AVX-512F (512b)"],
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"AVX512CD" => [ 65, "AVX-512 Conflict Detection"],
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"AVX512ER" => [ 66, "AVX-512 Exponential and Reciprocal"],
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"AVX512PF" => [ 67, "AVX-512 Prefetch"],
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"MPX" => [ 68 ,"MPX"],
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"SHA" => [ 69 ,"SHA"],
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"PREFETCHWT1" => [ 70 ,"PREFETCHWT1"],
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"AVX512VL" => [ 71, "AVX-512 Vector Length Orthogonality"],
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"AVX512DQ" => [ 72, "AVX-512 Dword and Qword"],
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"AVX512BW" => [ 73, "AVX-512 Byte and Word"],
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"AVX512IFMA" => [ 74, "AVX-512 IFMA instructions"],
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"AVX512VBMI" => [ 75, "AVX-512 VBMI instructions"],
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"VEX" => [ 94, "VEX or XOP encoded instruction"],
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"EVEX" => [ 95, "EVEX encoded instruction"],
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#
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# dword bound, index 3 - cpu type flags
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#
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# The CYRIX and AMD flags should have the highest bit values; the
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# disassembler selection algorithm depends on it.
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#
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"8086" => [ 96, "8086"],
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"186" => [ 97, "186+"],
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"286" => [ 98, "286+"],
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"386" => [ 99, "386+"],
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"486" => [100, "486+"],
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"PENT" => [101, "Pentium"],
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"P6" => [102, "P6"],
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"KATMAI" => [103, "Katmai"],
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"WILLAMETTE" => [104, "Willamette"],
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"PRESCOTT" => [105, "Prescott"],
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"X86_64" => [106, "x86-64 (long or legacy mode)"],
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"NEHALEM" => [107, "Nehalem"],
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"WESTMERE" => [108, "Westmere"],
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"SANDYBRIDGE" => [109, "Sandy Bridge"],
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"FUTURE" => [110, "Future processor (not yet disclosed)"],
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"IA64" => [111, "IA64 (in x86 mode)"],
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"CYRIX" => [126, "Cyrix-specific"],
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"AMD" => [127, "AMD-specific"],
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);
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my %insns_flag_hash = ();
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my @insns_flag_values = ();
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my $iflag_words;
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sub get_flag_words() {
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my $max = -1;
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foreach my $key (keys(%insns_flag_bit)) {
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if (${$insns_flag_bit{$key}}[0] > $max) {
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$max = ${$insns_flag_bit{$key}}[0];
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}
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}
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return int($max/32)+1;
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}
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sub insns_flag_index(@) {
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return undef if $_[0] eq "ignore";
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my @prekey = sort(@_);
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my $key = join("", @prekey);
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if (not defined($insns_flag_hash{$key})) {
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my @newkey = (0) x $iflag_words;
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for my $i (@prekey) {
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die "No key for $i\n" if not defined($insns_flag_bit{$i});
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$newkey[$insns_flag_bit{$i}[0]/32] |=
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(1 << ($insns_flag_bit{$i}[0] % 32));
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}
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my $str = join(',', map { sprintf("UINT32_C(0x%08x)",$_) } @newkey);
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push @insns_flag_values, $str;
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$insns_flag_hash{$key} = $#insns_flag_values;
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}
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return $insns_flag_hash{$key};
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}
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sub write_iflaggen_h() {
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print STDERR "Writing iflaggen.h ...\n";
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open(N, ">iflaggen.h") or die "$0: $!\n";
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print N "/* This file is auto-generated. Don't edit. */\n";
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print N "#ifndef NASM_IFLAGGEN_H\n";
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print N "#define NASM_IFLAGGEN_H 1\n\n";
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foreach my $key (sort { $insns_flag_bit{$a}[0] <=> $insns_flag_bit{$b}[0] } keys(%insns_flag_bit)) {
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print N sprintf("#define IF_%-16s %3d /* %-64s */\n",
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$key, $insns_flag_bit{$key}[0], $insns_flag_bit{$key}[1]);
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}
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print N "\n";
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print N "typedef struct {\n";
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printf N " uint32_t field[%d];\n", $iflag_words;
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print N "} iflag_t;\n";
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print N "\n";
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printf N "extern const iflag_t insns_flags[%d];\n\n",
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$#insns_flag_values + 1;
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print N "#endif /* NASM_IFLAGGEN_H */\n";
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close N;
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}
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sub write_iflag_c() {
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print STDERR "Writing iflag.c ...\n";
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open N, ">iflag.c";
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print N "/* This file is auto-generated. Don't edit. */\n";
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print N "#include \"iflag.h\"\n\n";
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print N "/* Global flags referenced from instruction templates */\n";
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printf N "const iflag_t insns_flags[%d] = {\n",
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$#insns_flag_values + 1;
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foreach my $i (0 .. $#insns_flag_values) {
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print N sprintf(" /* %4d */ {{ %s }},\n", $i, $insns_flag_values[$i]);
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}
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print N "};\n\n";
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close N;
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}
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$iflag_words = get_flag_words();
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1;
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