d2de48925e
Add test case for smacro descent from bug 3392586. Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
8 lines
259 B
NASM
8 lines
259 B
NASM
bits 32
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%define CACHE_SIZE 32
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%define MAXHEIGHT 1024
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%define DPS_MAXSPANS MAXHEIGHT+1
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%define spanpackage_t_size 32
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%define SPAN_SIZE (((DPS_MAXSPANS + 1 + ((CACHE_SIZE - 1) / spanpackage_t_size)) + 1) * spanpackage_t_size)
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D_PolysetDraw:
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sub esp,SPAN_SIZE
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