d85a6101d7
The a64 instruction patterns would incorrectly force REX to zero at a point where REX prefixes have already been assigned. This is not only incorrect in case of instructions which can use high registers, but it causes an assertion failure. It happened to work for J*CXZ and LOOP*. Reported-by: Philip Lantz <philip.lantz@intel.com> Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
22 lines
342 B
NASM
22 lines
342 B
NASM
bits 64
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start:
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invlpga eax,ecx
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invlpga rax,ecx
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jecxz start
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jrcxz start
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loop start,ecx
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loop start,rcx
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loope start,ecx
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loope start,rcx
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loopz start,ecx
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loopz start,rcx
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loopne start,ecx
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loopne start,rcx
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loopnz start,ecx
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loopnz start,rcx
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clzero eax
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clzero rax
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movdir64b eax,[edi]
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movdir64b rax,[rdi]
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umonitor eax
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umonitor rax
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