e56c2dc5b7
Break the instruction processing if there are impossible combinations of Sx flags and operand sizes. If the intent is to always require explicit sizes, use the SX flag. The INSERTPS instruction pattern was explicitly wrong, the rest of these are nuisance fixes. TODO: fix the disassembler to be able to exclude patterns where these bits don't matter. Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
15 lines
269 B
NASM
15 lines
269 B
NASM
bits 64
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movhpd xmm0,[rdi+2]
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movhpd xmm0,qword [rdi+2]
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movhpd [rsi+3],xmm1
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movhpd qword [rsi+3],xmm1
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vmovhpd xmm2,xmm1,[rax+4]
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vmovhpd xmm2,xmm1,qword [rax+4]
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vmovhpd xmm3,[rax+4]
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vmovhpd xmm3,qword [rax+4]
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vmovhpd [rcx+5],xmm4
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vmovhpd qword [rcx+5],xmm4
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