7f688841ce
AMD documents this instruction with an rax operand. The error behavior implies this is an address-size-sensitive instruction. Add support for specifying the explicit operand, but consistent with normal ndisasm behavior, don't disassemble the implicit operand. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
26 lines
221 B
NASM
26 lines
221 B
NASM
bits 16
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clzero
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clzero ax
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clzero eax
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%ifdef ERROR
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clzero rax
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%endif
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bits 32
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clzero
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clzero ax
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clzero eax
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%ifdef ERROR
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clzero rax
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%endif
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bits 64
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clzero
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%ifdef ERROR
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clzero ax
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%endif
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clzero eax
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clzero rax
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