2 commits

Author	SHA1	Message	Date
H. Peter Anvin	bebf220ba9	Complete the altreg set with "r0h".."r3h".	2007-12-10 15:36:39 -08:00
H. Peter Anvin	e55c836b5a	Document naming of registers in 64-bit mode ... Intel's docs diverge from AMD's docs (MASM follow AMD's docs); formally document what we're doing and include a file of macros in case someone wants to use alternate names.	2007-12-10 15:35:28 -08:00