Fix inefficient encoding of MPX instructions
BNDMK, BNDLDX, and BNDSTX are split-SIB (MIB) instructions, but do *not* require a SIB encoding. However, TILELOAD* and TILESTORE* *do* require a SIB in all cases. Split the MIB flag into MIB (split address) and SIB (SIB required) flags. This fixes travis test mpx. Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
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7839766663
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d988ce719c
5 changed files with 27 additions and 19 deletions
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@ -1226,7 +1226,7 @@ static int64_t calcsize(int32_t segment, int64_t offset, int bits,
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enum ea_type eat;
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uint8_t hleok = 0;
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bool lockcheck = true;
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enum reg_enum mib_index = R_none; /* For a separate index MIB reg form */
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enum reg_enum mib_index = R_none; /* For a separate index reg form */
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const char *errmsg;
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ins->rex = 0; /* Ensure REX is reset */
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@ -1262,7 +1262,7 @@ static int64_t calcsize(int32_t segment, int64_t offset, int bits,
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break;
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case4(014):
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/* this is an index reg of MIB operand */
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/* this is an index reg of a split SIB operand */
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mib_index = opx->basereg;
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break;
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@ -1592,6 +1592,10 @@ static int64_t calcsize(int32_t segment, int64_t offset, int bits,
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}
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}
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/* SIB encoding required */
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if (itemp_has(temp, IF_SIB))
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opy->eaflags |= EAF_SIB;
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if (process_ea(opy, &ea_data, bits,
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rfield, rflags, ins, &errmsg) != eat) {
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nasm_nonfatal("%s", errmsg);
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@ -2813,9 +2817,8 @@ static enum ea_type process_ea(operand *input, ea *output, int bits,
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}
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}
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if (bits == 64 &&
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!(IP_REL & ~input->type) && (eaflags & EAF_MIB)) {
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*errmsg = "RIP-relative addressing is prohibited for MIB";
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if (bits == 64 && !(IP_REL & ~input->type) && (eaflags & EAF_SIB)) {
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*errmsg = "instruction requires SIB encoding, cannot be RIP-relative";
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goto err;
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}
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@ -2824,7 +2827,7 @@ static enum ea_type process_ea(operand *input, ea *output, int bits,
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input->disp_size != (addrbits != 16 ? 32 : 16)))
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nasm_warn(WARN_OTHER, "displacement size ignored on absolute address");
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if ((eaflags & EAF_MIB) || (bits == 64 && (~input->type & IP_REL))) {
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if ((eaflags & EAF_SIB) || (bits == 64 && (~input->type & IP_REL))) {
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output->sib_present = true;
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output->sib = GEN_SIB(0, 4, 5);
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output->bytes = 4;
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@ -3002,7 +3005,7 @@ static enum ea_type process_ea(operand *input, ea *output, int bits,
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bt = it, bx = ix, it = -1, ix = 0;
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}
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if (eaflags & EAF_MIB) {
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/* only for mib operands */
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/* MIB/split-SIB encoding */
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if (it == -1 && (hb == b && ht == EAH_NOTBASE)) {
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/*
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* make a single reg index [reg*1].
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@ -3043,7 +3046,7 @@ static enum ea_type process_ea(operand *input, ea *output, int bits,
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output->rex |= rexflags(it, ix, REX_X);
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output->rex |= rexflags(bt, bx, REX_B);
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if (it == -1 && (bt & 7) != REG_NUM_ESP && !(eaflags & EAF_MIB)) {
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if (it == -1 && (bt & 7) != REG_NUM_ESP && !(eaflags & EAF_SIB)) {
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/* no SIB needed */
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int mod, rm;
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@ -37,6 +37,9 @@ useful to debug NASM crashes. See \k{opt-L}.
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\b Fix the \c{__float80e__} and \c{__float128h__} conversions, which
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would return the wrong bytes of the result.
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\b Fix inefficient encoding of the \c{BNDMK}, \c{BNDLDX}, and
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\c{BNDSTX} instructions under certain circumstances.
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\S{cl-2.15.03} Version 2.15.03
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\b Add instructions from the Intel Instruction Set Extensions and
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@ -553,13 +553,14 @@ enum prefixes { /* instruction prefixes */
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};
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enum ea_flags { /* special EA flags */
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EAF_BYTEOFFS = 1, /* force offset part to byte size */
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EAF_WORDOFFS = 2, /* force offset part to [d]word size */
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EAF_TIMESTWO = 4, /* really do EAX*2 not EAX+EAX */
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EAF_REL = 8, /* IP-relative addressing */
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EAF_ABS = 16, /* non-IP-relative addressing */
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EAF_FSGS = 32, /* fs/gs segment override present */
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EAF_MIB = 64 /* mib operand */
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EAF_BYTEOFFS = 1, /* force offset part to byte size */
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EAF_WORDOFFS = 2, /* force offset part to [d]word size */
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EAF_TIMESTWO = 4, /* really do EAX*2 not EAX+EAX */
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EAF_REL = 8, /* IP-relative addressing */
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EAF_ABS = 16, /* non-IP-relative addressing */
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EAF_FSGS = 32, /* fs/gs segment override present */
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EAF_MIB = 64, /* mib operand */
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EAF_SIB = 128 /* SIB encoding obligatory */
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};
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enum eval_hint { /* values for `hinttype' */
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@ -36,7 +36,8 @@ if_("LOCK", "Lockable if operand 0 is memory");
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if_("NOLONG", "Not available in long mode");
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if_("LONG", "Long mode");
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if_("NOHLE", "HLE prefixes forbidden");
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if_("MIB", "disassemble with split EA");
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if_("MIB", "split base/index EA");
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if_("SIB", "SIB encoding required");
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if_("BND", "BND (0xF2) prefix available");
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if_("UNDOC", "Undocumented");
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if_("HLE", "HLE prefixed");
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@ -6049,10 +6049,10 @@ TDPBSSD tmmreg,tmmreg,tmmreg [rmv: vex.128.f2.0f38.w0 5e /r] AMXINT8,FUTURE,L
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TDPBSUD tmmreg,tmmreg,tmmreg [rmv: vex.128.f3.0f38.w0 5e /r] AMXINT8,FUTURE,LONG
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TDPBUSD tmmreg,tmmreg,tmmreg [rmv: vex.128.66.0f38.w0 5e /r] AMXINT8,FUTURE,LONG
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TDPBUUD tmmreg,tmmreg,tmmreg [rmv: vex.128.np.0f38.w0 5e /r] AMXINT8,FUTURE,LONG
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TILELOADD tmmreg,mem [rm: vex.128.f2.0f38.w0 4b /r] AMXTILE,MIB,FUTURE,SX,LONG
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TILELOADDT1 tmmreg,mem [rm: vex.128.66.0f38.w0 4b /r] AMXTILE,MIB,FUTURE,SX,LONG
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TILELOADD tmmreg,mem [rm: vex.128.f2.0f38.w0 4b /r] AMXTILE,MIB,SIB,FUTURE,SX,LONG
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TILELOADDT1 tmmreg,mem [rm: vex.128.66.0f38.w0 4b /r] AMXTILE,MIB,SIB,FUTURE,SX,LONG
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TILERELEASE void [ vex.128.np.0f38.w0 49 c0] AMXTILE,FUTURE,LONG
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TILESTORED mem,tmmreg [mr: vex.128.f3.0f38.w0 4b /r] AMXTILE,MIB,FUTURE,SX,LONG
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TILESTORED mem,tmmreg [mr: vex.128.f3.0f38.w0 4b /r] AMXTILE,MIB,SIB,FUTURE,SX,LONG
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TILEZERO tmmreg [r: vex.128.f2.0f38.w0 49 /3r0] AMXTILE,FUTURE,LONG
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;# Systematic names for the hinting nop instructions
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