insns: Remove pushseg/popseg internal bytecodes
This patch is getting rid of the following bytecodes 'pushseg','popseg','pushseg2','popseg2' and simplifies overall code. [gorcunov@: a few style fixes] Signed-off-by: Ben Rudiak-Gould <benrudiak@gmail.com> Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
This commit is contained in:
Ben Rudiak-Gould
Cyrill Gorcunov
parent
83e6924e1a
commit
d1ac29a3cc
6 changed files with 58 additions and 119 deletions
50
assemble.c
50
assemble.c
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@ -124,10 +124,6 @@
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* \340 - reserve <operand 0> bytes of uninitialized storage.
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* Operand 0 had better be a segmentless constant.
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* \341 - this instruction needs a WAIT "prefix"
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* \344,\345 - the PUSH/POP (respectively) codes for CS, DS, ES, SS
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* (POP is never used for CS) depending on operand 0
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* \346,\347 - the second byte of PUSH/POP codes for FS, GS, depending
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* on operand 0
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* \360 - no SSE prefix (== \364\331)
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* \361 - 66 SSE prefix (== \366\331)
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* \362 - F2 SSE prefix (== \364\332)
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@ -1050,10 +1046,6 @@ static int64_t calcsize(int32_t segment, int64_t offset, int bits,
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ins->prefixes[PPS_WAIT] = P_WAIT;
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break;
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case4(0344):
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length++;
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break;
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case 0360:
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break;
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@ -1602,48 +1594,6 @@ static void gencode(int32_t segment, int64_t offset, int bits,
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case 0341:
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break;
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case 0344:
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case 0345:
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bytes[0] = c & 1;
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switch (ins->oprs[0].basereg) {
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case R_CS:
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bytes[0] += 0x0E;
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break;
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case R_DS:
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bytes[0] += 0x1E;
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break;
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case R_ES:
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bytes[0] += 0x06;
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break;
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case R_SS:
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bytes[0] += 0x16;
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break;
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default:
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errfunc(ERR_PANIC,
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"bizarre 8086 segment register received");
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}
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out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
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offset++;
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break;
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case 0346:
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case 0347:
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bytes[0] = c & 1;
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switch (ins->oprs[0].basereg) {
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case R_FS:
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bytes[0] += 0xA0;
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break;
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case R_GS:
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bytes[0] += 0xA8;
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break;
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default:
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errfunc(ERR_PANIC,
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"bizarre 386 segment register received");
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}
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out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
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offset++;
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break;
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case 0360:
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break;
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75
disasm.c
75
disasm.c
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@ -112,50 +112,43 @@ static uint64_t getu64(uint8_t *data)
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/* Important: regval must already have been adjusted for rex extensions */
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static enum reg_enum whichreg(opflags_t regflags, int regval, int rex)
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{
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size_t i;
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static const struct {
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opflags_t flags;
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enum reg_enum reg;
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} specific_registers[] = {
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{REG_AL, R_AL},
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{REG_AX, R_AX},
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{REG_EAX, R_EAX},
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{REG_RAX, R_RAX},
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{REG_DL, R_DL},
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{REG_DX, R_DX},
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{REG_EDX, R_EDX},
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{REG_RDX, R_RDX},
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{REG_CL, R_CL},
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{REG_CX, R_CX},
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{REG_ECX, R_ECX},
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{REG_RCX, R_RCX},
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{FPU0, R_ST0},
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{XMM0, R_XMM0},
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{YMM0, R_YMM0},
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{REG_ES, R_ES},
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{REG_CS, R_CS},
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{REG_SS, R_SS},
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{REG_DS, R_DS},
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{REG_FS, R_FS},
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{REG_GS, R_GS}
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};
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if (!(regflags & (REGISTER|REGMEM)))
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return 0; /* Registers not permissible?! */
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regflags |= REGISTER;
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if (!(REG_AL & ~regflags))
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return R_AL;
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if (!(REG_AX & ~regflags))
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return R_AX;
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if (!(REG_EAX & ~regflags))
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return R_EAX;
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if (!(REG_RAX & ~regflags))
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return R_RAX;
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if (!(REG_DL & ~regflags))
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return R_DL;
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if (!(REG_DX & ~regflags))
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return R_DX;
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if (!(REG_EDX & ~regflags))
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return R_EDX;
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if (!(REG_RDX & ~regflags))
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return R_RDX;
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if (!(REG_CL & ~regflags))
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return R_CL;
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if (!(REG_CX & ~regflags))
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return R_CX;
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if (!(REG_ECX & ~regflags))
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return R_ECX;
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if (!(REG_RCX & ~regflags))
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return R_RCX;
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if (!(FPU0 & ~regflags))
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return R_ST0;
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if (!(XMM0 & ~regflags))
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return R_XMM0;
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if (!(YMM0 & ~regflags))
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return R_YMM0;
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if (!(REG_CS & ~regflags))
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return (regval == 1) ? R_CS : 0;
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if (!(REG_DESS & ~regflags))
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return (regval == 0 || regval == 2
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|| regval == 3 ? nasm_rd_sreg[regval] : 0);
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if (!(REG_FSGS & ~regflags))
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return (regval == 4 || regval == 5 ? nasm_rd_sreg[regval] : 0);
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if (!(REG_SEG67 & ~regflags))
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return (regval == 6 || regval == 7 ? nasm_rd_sreg[regval] : 0);
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for (i = 0; i < ARRAY_SIZE(specific_registers); i++)
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if (!(specific_registers[i].flags & ~regflags))
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return specific_registers[i].reg;
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/* All the entries below look up regval in an 16-entry array */
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if (regval < 0 || regval > 15)
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@ -830,10 +823,6 @@ static int matches(const struct itemplate *t, uint8_t *data,
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dwait = 0;
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break;
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case4(0344):
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ins->oprs[0].basereg = (*data++ >> 3) & 7;
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break;
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case 0360:
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if (prefix->osp || prefix->rep)
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return false;
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16
insns.dat
16
insns.dat
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@ -1005,9 +1005,12 @@ POP reg64 [r: o64nw 58+r] X64
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POP rm16 [m: o16 8f /0] 8086
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POP rm32 [m: o32 8f /0] 386,NOLONG
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POP rm64 [m: o64nw 8f /0] X64
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POP reg_es [-: 07] 8086,NOLONG
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POP reg_cs [-: 0f] 8086,UNDOC,ND
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POP reg_dess [-: popseg] 8086,NOLONG
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POP reg_fsgs [-: 0f popseg2] 386
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POP reg_ss [-: 17] 8086,NOLONG
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POP reg_ds [-: 1f] 8086,NOLONG
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POP reg_fs [-: 0f a1] 386
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POP reg_gs [-: 0f a9] 386
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POPA void [ odf 61] 186,NOLONG
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POPAD void [ o32 61] 386,NOLONG
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POPAW void [ o16 61] 186,NOLONG
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@ -1054,9 +1057,12 @@ PUSH reg64 [r: o64nw 50+r] X64
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PUSH rm16 [m: o16 ff /6] 8086
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PUSH rm32 [m: o32 ff /6] 386,NOLONG
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PUSH rm64 [m: o64nw ff /6] X64
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PUSH reg_cs [-: pushseg] 8086,NOLONG
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PUSH reg_dess [-: pushseg] 8086,NOLONG
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PUSH reg_fsgs [-: 0f pushseg2] 386
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PUSH reg_es [-: 06] 8086,NOLONG
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PUSH reg_cs [-: 0e] 8086,NOLONG
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PUSH reg_ss [-: 16] 8086,NOLONG
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PUSH reg_ds [-: 1e] 8086,NOLONG
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PUSH reg_fs [-: 0f a0] 386
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PUSH reg_gs [-: 0f a8] 386
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PUSH imm8 [i: 6a ib,s] 186
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PUSH sbyteword16 [i: o16 6a ib,s] 186,AR0,SZ,ND
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PUSH imm16 [i: o16 68 iw] 186,AR0,SZ
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12
insns.pl
12
insns.pl
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@ -608,14 +608,6 @@ sub startseq($$) {
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return addprefix($prefix, $c1..($c1+15));
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} elsif ($c0 == 0 || $c0 == 0340) {
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return $prefix;
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} elsif ($c0 == 0344) {
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return addprefix($prefix, 0x06, 0x0E, 0x16, 0x1E);
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} elsif ($c0 == 0345) {
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return addprefix($prefix, 0x07, 0x17, 0x1F);
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} elsif ($c0 == 0346) {
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return addprefix($prefix, 0xA0, 0xA8);
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} elsif ($c0 == 0347) {
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return addprefix($prefix, 0xA1, 0xA9);
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} elsif (($c0 & ~3) == 0260 || $c0 == 0270) {
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my $c,$m,$wlp;
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$m = shift(@codes);
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@ -694,10 +686,6 @@ sub byte_code_compile($$) {
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'!asp' => 0365,
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'f2i' => 0332, # F2 prefix, but 66 for operand size is OK
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'f3i' => 0333, # F3 prefix, but 66 for operand size is OK
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'pushseg' => 0344,
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'popseg' => 0345,
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'pushseg2' => 0346,
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'popseg2' => 0347,
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'mustrep' => 0336,
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'mustrepne' => 0337,
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'rex.l' => 0334,
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14
opflags.h
14
opflags.h
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@ -191,10 +191,16 @@ typedef uint64_t opflags_t;
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#define REG_DREG (GEN_SUBCLASS(2) | REG_CLASS_CDT | BITS32 | REGISTER) /* DRn */
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#define REG_TREG (GEN_SUBCLASS(3) | REG_CLASS_CDT | BITS32 | REGISTER) /* TRn */
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#define REG_SREG ( REG_CLASS_SREG | BITS16 | REGISTER) /* any segment register */
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#define REG_CS (GEN_SUBCLASS(1) | REG_CLASS_SREG | BITS16 | REGISTER) /* CS */
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#define REG_DESS (GEN_SUBCLASS(2) | REG_CLASS_SREG | BITS16 | REGISTER) /* DS, ES, SS */
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#define REG_FSGS (GEN_SUBCLASS(3) | REG_CLASS_SREG | BITS16 | REGISTER) /* FS, GS */
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#define REG_SEG67 (GEN_SUBCLASS(4) | REG_CLASS_SREG | BITS16 | REGISTER) /* Unimplemented segment registers */
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/* Segment registers */
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#define REG_ES (GEN_SUBCLASS(0) | GEN_SUBCLASS(2) | REG_CLASS_SREG | BITS16 | REGISTER) /* ES */
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#define REG_CS (GEN_SUBCLASS(1) | GEN_SUBCLASS(2) | REG_CLASS_SREG | BITS16 | REGISTER) /* CS */
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#define REG_SS (GEN_SUBCLASS(0) | GEN_SUBCLASS(3) | REG_CLASS_SREG | BITS16 | REGISTER) /* SS */
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#define REG_DS (GEN_SUBCLASS(1) | GEN_SUBCLASS(3) | REG_CLASS_SREG | BITS16 | REGISTER) /* DS */
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#define REG_FS (GEN_SUBCLASS(0) | GEN_SUBCLASS(4) | REG_CLASS_SREG | BITS16 | REGISTER) /* FS */
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#define REG_GS (GEN_SUBCLASS(1) | GEN_SUBCLASS(4) | REG_CLASS_SREG | BITS16 | REGISTER) /* GS */
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#define REG_FSGS ( GEN_SUBCLASS(4) | REG_CLASS_SREG | BITS16 | REGISTER) /* FS or GS */
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#define REG_SEG67 ( GEN_SUBCLASS(5) | REG_CLASS_SREG | BITS16 | REGISTER) /* Unimplemented segment registers */
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/* Special GPRs */
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#define REG_SMASK SUBCLASS_MASK /* a mask for the following */
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10
regs.dat
10
regs.dat
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@ -86,12 +86,12 @@ r8-15d REG32NA reg32 8
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r8-15 REG64NA reg64 8
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# Segment registers
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es REG_ES sreg 0
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cs REG_CS sreg 1
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ds REG_DESS sreg 3
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es REG_DESS sreg 0
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ss REG_DESS sreg 2
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fs REG_FSGS sreg 4
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gs REG_FSGS sreg 5
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ss REG_SS sreg 2
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ds REG_DS sreg 3
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fs REG_FS sreg 4
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gs REG_GS sreg 5
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segr6-7 REG_SEG67 sreg 6
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# Control registers
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